Datasheet.kr   

W3DG7232V-D2 데이터시트 PDF




White Electronic Designs에서 제조한 전자 부품 W3DG7232V-D2은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 W3DG7232V-D2 자료 제공

부품번호 W3DG7232V-D2 기능
기능 SDRAM UNBUFFERED
제조업체 White Electronic Designs
로고 White Electronic Designs 로고


W3DG7232V-D2 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



전체 9 페이지수

미리보기를 사용할 수 없습니다

W3DG7232V-D2 데이터시트, 핀배열, 회로
White Electronic Designs
W3DG7232V-D2
PRELIMINARY*
256MB – 32Mx72 SDRAM, REGISTER and SPD, w/PLL
FEATURES
Burst Mode Operation
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
Fully synchronous: All signals are registered on the positive
edge of the system clock
Programmable Burst Lengths: 1, 2, 4, 8 or Full Page
3.3V ± 0.3V Power Supply
168 Pin DIMM JEDEC
NOTE: Consult factory for availability of:
www.DataShLeeade-Ftr4eeUPr.ocduoctsm
• Vendor source control options
• Industrial temperature options
DESCRIPTION
The W3DG7232V is a 32Mx72 synchronous DRAM module
which consists of nine 32Meg x 8 SDRAM components
in TSOP II package, two 18 bit Drive ICs for input control
signal and one 2Kb EEPROM in an 8 pin TSSOP package
for Serial Presence Detect which are mounted on a 168
pin DIMM multilayer FR4 Substrate.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PIN FRONT PIN BACK PIN FRONT PIN BACK PIN
1 VSS 29 DQMB1 57 DQ18 85 VSS 113
2 DQ0 30 CS0# 58 DQ19 86 DQ32 114
3 DQ1 31 DNU 59 VCC 87 DQ33 115
4 DQ2 32 VSS 60 DQ20 88 DQ34 116
5 DQ3 33 A0 61 NC 89 DQ35 117
6 VCC 34 A2 62 *VREF 90 VCC 118
7 DQ4 35 A4 63 *CKE1 91 DQ36 119
8 DQ5 36 A6 64 VSS 92 DQ37 120
9 DQ6 37 A8 65 DQ21 93 DQ38 121
10 DQ7 38 A10/AP 66 DQ22 94 DQ39 122
11 DQ8 39 BA1 67 DQ23 95 DQ40 123
12 VSS 40 VCC 68 VSS 96 VSS 124
13 DQ9 41 VCC 69 DQ24 97 DQ41 125
14 DQ10 42 CK0 70 DQ25 98 DQ42 126
15 DQ11 43 VSS 71 DQ26 99 DQ43 127
16 DQ12 44 DNU 72 DQ27 100 DQ44 128
17 DQ13 45 CS2# 73 VCC 101 DQ45 129
18 VCC 46 DQMB2 74 DQ28 102 VCC 130
19 DQ14 47 DQMB3 75 DQ29 103 DQ46 131
20 DQ15 48 DNU 76 DQ30 104 DQ47 132
21 CB0 49 VCC 77 DQ31 105 CB4 133
22 CB1 50 NC 78 VSS 106 CB5 134
23 VSS 51 NC 79 *CK2 107 VSS 135
24 NC 52 CB2 80 NC 108 NC 136
25 NC 53 CB3 81 NC 109 NC 137
26 VCC 54 VSS 82 **SDA 110 VCC 138
27 WE# 55 DQ16 83 **SCL 111 CAS# 139
28 DQMB0 56 DQ17 84 VCC 112 DQMB4 140
BACK
DQMB5
*CS1#
RAS#
VSS
A1
A3
A5
A7
A9
BA0
A11
VCC
*CK1
A12
VSS
CKE0
*CS3#
DQMB6
DQMB7
*A13
VCC
NC
NC
CB6
CB7
VSS
DQ48
DQ49
PIN
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
BACK
DQ50
DQ51
VCC
DQ52
NC
*VREF
REGE
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
*CK3
NC
**SA0
**SA1
**SA2
VCC
PIN NAMES
A0 – A12
BA0-1
DQ0-63
CB0-7
CK0
CKE0
CS0#, CS2#
RAS#
CAS#
WE#
DQMB0-7
VCC
VSS
*VREF
REGE
SDA
SCL
SA0-2
DNU
NC
Address Input (Multiplexed)
Select Bank
Data Input/Output
Check Bit (Data-In/Data-Out)
Clock Input
Clock Enable Input
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
DQMB
Power Supply (3.3V)
Ground
Power Supply for Reference
Register Enable
Serial Data I/O
Serial Clock
Address in EEPROM
Do Not Use
No Connect
* These pins are not used in this module.
** These pins should be NC in the system which does
not support SPD.
February 2005
Rev. 1
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com




W3DG7232V-D2 pdf, 반도체, 판매, 대치품
White Electronic Designs
W3DG7232V-D2
PRELIMINARY
Parameters
Operating Current
(One bank active)
Precharge Standby Current
in Power Down Mode
Active standby in current non power-
down mode
Operating current (Burst mode)
Refresh current
www.DSaelftarefSrehshecuerrte4ntU.com
Notes: 1. Measured with outputs open.
2. Refresh period is 64ms.
3. Measured with 1 PLL & 2 Drive ICs.
OPERATING CURRENT CHARACTERISTICS
VCC = 3.3V, 0°C TA 70°C
Symbol
Conditions
Versions
133/100
ICC1 Burst Length = 1
tRC ≥ tRC(min)
IOL = 0mA
ICC2P
CKE ≤ VIL(max), tCC = 10ns
900
18
ICC3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are charged one time during 20ns
ICC4 Io = mA
Page burst
4 Banks activated
tCCD = 2CLK
ICC5 tRC ≥ tRC(min)
ICC6 CKE ≤ 0.2V
270
990
1980
27
Units
mA
mA
mA
mA
mA
mA
Note
1
3
3
1
2
3
February 2005
Rev. 1
4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

4페이지










W3DG7232V-D2 전자부품, 판매, 대치품
White Electronic Designs
W3DG7232V-D2
PRELIMINARY
Notes
1. All voltages referenced to VSS.
2. This parameter is sampled. VCC, VCCQ = +3.3V; TA = 25°C; pin under test biased at
1.4V; f = 1 MHz.
3. IDD is dependent on output loading and cycle rates. Specified values are obtained
with mini-mum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
operation over the full temperature range is ensured.
6. An initial pause of 100µs is required after power-up, followed by two AUTO
REFRESH commands, before proper device operation is ensured. (VCC and VCCQ
must be powered up simultaneously. VSS and VSSQ must be at same potential.) The
two AUTO REFRESH command wake-ups should be repeated any time the tREF
refresh requirement is exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE must
transit between VIH and VIL (or between VIL and VIH) in a mono-tonic manner.
9. Outputs measured at 1.5V with equivalent load:
Q
50pF
www.1D0.attHaZ dSefinhees tehett4imUe a.t cwhoicmh the output achieves the open circuit condition; it is not
a reference to VOH or VOL. The last valid data element will meet tOH before going
High-Z.
11. AC timing and IDD tests have VIL = 0V and VIH = 3V with timing referenced to 1.5V
crossover point. If the input transition time is longer than 1ns, then the timing is
referenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point.
12. Other input signals are allowed to transition no more than once every two clocks
and are other-wise at valid VIH or VIL levels.
13. IDD specifications are tested after the device is properly initialized.
14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum
cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at
minimum cycle rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC functionality and are not dependent on
any timing parameter.
18. The IDD current will increase or decrease proportionally according to the amount of
frequency alteration for the test condition.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on tCK = 10ns for 10, and tCK = 7.5ns for 7 and 7.5.
22. VIH overshoot: VIH (MAX) = VCCQ + 2V for a pulse width ≤ 3ns, and the pulse width
cannot be greater than one third of the cycle rate. VIL under-shoot: VIL (MIN) = -2V
for a pulse width ≤ 3ns.
23. The clock frequency must remain constant (stable clock is defined as a signal
cycling within timing constraints specified for the clock pin) during access or
precharge states (READ, WRITE, including tWR, and PRECHARGE commands).
CKE may be used to reduce the data rate.
24. Auto precharge mode only. The precharge timing budget (tRP) begins 7ns for 7;
7.5ns for 7.5 and 7.5ns for 10 after the first clock delay, after the last WRITE is
executed. May not exceed limit set for precharge mode.
25. Precharge mode only.
26. JEDEC and PC133, PC100 specify three clocks.
27. tAC for 7/7.5 at CL = 3 with no load is 4.6ns and is guaranteed by design.
28. Parameter guaranteed by design.
February 2005
Rev. 1
7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

7페이지


구       성 총 9 페이지수
다운로드[ W3DG7232V-D2.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
W3DG7232V-D1

SDRAM UNBUFFERED

White Electronic Designs
White Electronic Designs
W3DG7232V-D2

SDRAM UNBUFFERED

White Electronic Designs
White Electronic Designs

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵