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PDF 89C51RC Data sheet ( Hoja de datos )
| Número de pieza | 89C51RC | |
| Descripción | AT89C51RC | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Compatible with MCS®-51 Products
• 32K Bytes of Reprogrammable Flash Memory
• Endurance: 1000 Write/Erase Cycles
• 4V to 5.5V Operating Range
• Fully Static Operation: 0 Hz to 33 MHz
• Three-level Program Memory Lock
• 512 x 8-bit Internal RAM
• 32 Programmable I/O Lines
• Three 16-bit Timer/Counters
• Eight Interrupt Sources
• Programmable Serial Channel
www.Data•ShLeoetw4U-p.coowmer Idle and Power-down Modes
• Interrupt Recovery from Power-down Mode
• Hardware Watchdog Timer
• Dual Data Pointer
• Power-off Flag
• Green (Pb/Halide-free) Packaging Option
1. Description
The AT89C51RC is a low-power, high-performance CMOS 8-bit microcontroller with
32K bytes of Flash programmable read-only memory and 512 bytes of RAM. The
device is manufactured using Atmel’s high-density nonvolatile memory technology
and is compatible with the industry-standard 80C51 and 80C52 instruction set and
pinout. The on-chip Flash allows the program memory to be user programmed by a
conventional nonvolatile memory programmer. A total of 512 bytes of internal RAM
are available in the AT89C51RC. The 256-byte expanded internal RAM is accessed
via MOVX instructions after clearing bit 1 in the SFR located at address 8EH. The
other 256-byte RAM segment is accessed the same way as the Atmel AT89-series
and other 8052-compatible products. By combining a versatile 8-bit CPU with Flash
on a monolithic chip, the Atmel AT89C51RC is a powerful microcomputer which pro-
vides a highly-flexible and cost-effective solution to many embedded control
applications.
The AT89C51RC provides the following standard features: 32K bytes of Flash, 512
bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt
architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition,
the AT89C51RC is designed with static logic for operation down to zero frequency
and supports two software selectable power saving modes. The Idle Mode stops the
CPU while allowing the RAM, timer/counters, serial port, and interrupt system to con-
tinue functioning. The Power-down mode saves the RAM contents but freezes the
oscillator, disabling all other chip functions until the next external interrupt or hardware
reset.
8-bit
Microcontroller
with 32K Bytes
Flash
AT89C51RC
1920C–MICRO–03/05
1 page  
4.6 Port 3
AT89C51RC
Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can
sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter-
nal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low
will source current (IIL) because of the pull-ups.
Port 3 receives some control signals for Flash programming and verification.
Port 3 also serves the functions of various special features of the AT89C51RC, as shown in the
following table.
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Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Alternate Functions
RXD (serial input port)
TXD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (timer 0 external input)
T1 (timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
4.7 RST
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the
device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DISRTO
bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit
DISRTO, the RESET HIGH out feature is enabled.
4.8 ALE/PROG
Address Latch Enable is an output pulse for latching the low byte of the address during
accesses to external memory. This pin is also the program pulse input (PROG) during Flash
programming.
In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be
used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped dur-
ing each access to external data memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set,
ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high.
Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.
4.9 PSEN
Program Store Enable is the read strobe to external program memory.
When the AT89C51RC is executing code from external program memory, PSEN is activated
twice each machine cycle, except that two PSEN activations are skipped during each access to
external data memory.
1920C–MICRO–03/05
5
5 Page 
AT89C51RC
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With EXTRAM = 0, the ERAM is indirectly addressed, using the MOVX instruction in combina-
tion with any of the registers R0, R1 of the selected bank or DPTR. An access to ERAM will not
affect ports P0, P2, P3.6 (WR), and P3.7 (RD). For example, with EXTRAM = 0,
MOVX@R0, # data
where R0 contains 0A0H, accesses the ERAM at address 0A0H rather than external memory.
An access to external data memory locations higher than FFH (i.e. 0100H to FFFFH) will be per-
formed with the MOVX DPTR instructions in the same way as in the standard 80C51, i.e., with
P0 and P2 as data/address bus, and P3.6 and P3.7 as write and read timing signals (see Figure
7-1).
Figure 7-1.
Internal and External Data Memory Address (with EXTRAM = 0)
FF
ERAM
256 BYTES
FF
UPPER
128 BYTES
INTERNAL
RAM
80
FF
SPECIAL
FUNCTION
REGISTER
FFFF
EXTERNAL
DATA
MEMORY
80
LOWER
128 BYTES
INTERNAL
RAM
00 00
0100
0000
With EXTRAM = 1, MOVX @ Ri and MOVX@DPTR will be similar to the standard 80C51.
MOVX@Ri will provide an 8-bit address multiplexed with data on Port 0 and any output port pins
can be used to output higher-order address bits. This is to provide the external paging capability.
MOVX@DPTR will generate a 16-bit address. Port 2 outputs the high-order 8 address bits (the
contents of DP0H), while Port 0 multiplexes the low-order 8 address bits (the contents of DP0L)
with data. MOVX@Ri and MOVX@DPTR will generate either read or write signals on P3.6 (WR)
and P3.7 (RD).
The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM)
internal data memory. The stack may not be located in the ERAM.
8. Hardware Watchdog Timer (One-time Enabled with Reset-out)
The WDT is intended as a recovery method in situations where the CPU may be subjected to
software upsets. The WDT consists of a 13-bit counter and the WatchDog Timer Reset
(WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user
must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When
the WDT is enabled, it will increment every machine cycle while the oscillator is running. The
WDT timeout period is dependent on the external clock frequency. There is no way to disable
the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over-
flows, it will drive an output RESET HIGH pulse at the RST pin.
1920C–MICRO–03/05
11
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