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PDF PECL_RX Data sheet ( Hoja de datos )
| Número de pieza | PECL_RX | |
| Descripción | CMOS PECL Receiver | |
| Fabricantes | austriamicrosystems AG | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PECL_RX (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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ANALOG IP BLOCK
PECL_RX - CMOS PECL Receiver
DATA SHEET
PROCESS
C35B3 (0.35um)
www.DataSheet4U.com
FEATURES
! PECL_RX area: 0.1 mm2,
size: x = 300 µm y = 340 µm
! PERXBIAS
size: x = 382 µm y = 375 µm
! 3.3 V ±10% supply voltage
! 622 Mb/s transmission speed
! 1 ns max. propagation delay
! Power dissipation 23 mW at 3.3 V static without
PERXBIAS
! Junction temperature –40 - 125°C
! Output levels fully compatible with F100K PECL
Family
! Power down mode
DESCRIPTION
The PECL_RX is a 3.3 V PECL differential line receiver
featuring an operating frequency up to 311 MHz (622 Mb/s)
and accepting standard F100K levels (referred to the positive
supply).
The PECL_RX accepts (750 mV) differential input signals and
translates them to CMOS output levels.
With the companion line driver (PECL_TX ) it can be used for
high speed applications.
The cell PECL_RX requires the PERXBIAS cell for biasing.
PERXBIAS can drive up to 3 PECL_RX cells. An external
voltage reference must be used.
The PECL_RX can be set in power down mode.
Revision B, 10.09.02
Page 1 of 6
1 page  
Datasheet: PECL_RX - C35
APPLICATION
! High Speed Backplane Driver
! Complementary Clock Drivers
! Level Translator
! System Interconnects
! ATM Applications
TYPICAL APPLICATION1)
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! SDH Applications
! High-Resolution Imaging Applications
! Laser Printers
! Digital Copiers
VDDA
1 µF 100pF 22pF
external chip internal
SNAP BACK 6)
VDDA 1) 4)
VSSA 3)
VDD
1 µF 100pF
VSS 3)
22pF
VDDA 1)
VDD 4)
VT
50Ω
7)
7)
7)
DATA
50Ω transmission lines
DATAN
from transmitter
VDDA
+
2V
- 1 µF
VT
100pF
50Ω
VT
VSS 3) 4)
22pF
VSSA 3) 4)
VREF
1nF
VREF (external reference) 2)
180pF
SNAP BACK 6)
VSSA 3)
complementary
CMOS signals
(to digital core)
5)
1) Each power pin must have its own set of blocking capacitors.
2) An external reference must be used.
3) VSSA and VSS must be connected on the PCB level.
4) The two power pads can be bonded to one package pin (double bonding).
5) Two more PECL_RX cells can be driven with IREFxx of the PERXBIAS cell. If an output IREFxx is not used it must be left unconnected.
6) The PECL part of the chip has to be separated from the rest of the chip by use of snap backs (cell PWRCUT_DIG_P_SNAP_SNAP).
7) The cells VDD3R1P and VDD3R2P are not in the standard library, they are part of the IP-block.
Revision B, 10.09.02
Page 5 fo 6
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet PECL_RX.PDF ] | |
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