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PDF 46R22 Data sheet ( Hoja de datos )
| Número de pieza | 46R22 | |
| Descripción | HT46R22 | |
| Fabricantes | Holtek Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 46R22 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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HT46R22/HT46C22
8-Bit A/D Type MCU
www.DataSheet4U.com
Features
· Operating voltage:
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 4.5V~5.5V
· 19 bidirectional I/O lines (max.)
· 1 interrupt input shared with an I/O line
· 8-bit programmable timer/event counter with over-
flow interrupt and 7-stage prescaler
· On-chip crystal and RC oscillator
· Watchdog Timer
· 2048´14 program memory ROM
· 64´8 data memory RAM
· Supports PFD for sound generation
· HALT function and wake-up feature reduce power
consumption
· Up to 0.5ms instruction cycle with 8MHz system clock
at VDD=5V
· 6-level subroutine nesting
· 8 channels 9-bit resolution (8-bit accuracy) A/D con-
verter
· 1-channel (6+2)/(7+1)-bit PWM output shared with
two I/O lines
· Bit manipulation instruction
· 14-bit table read instruction
· 63 powerful instructions
· All instructions in one or two machine cycles
· Low voltage reset function
· I2C BUS (slave mode)
· 24-pin SKDIP/SOP package
General Description
The device is an 8-bit high performance RISC-like
microcontroller designed for multiple I/O product appli-
cations. It is particularly suitable for use in products
such as washing machine controllers and home appli-
ances. A HALT feature is included to reduce power con-
sumption.
I2C is a trademark of Philips Semiconductors
Rev. 1.10
1
October 2, 2002
1 page  
HT46R22/HT46C22
www.DataSheet4U.com
Symbol
Parameter
VIH1
Input High Voltage for I/O Ports,
TMR and INT
VIL2 Input Low Voltage (RES)
VIH2
VLVR
IOL
Input High Voltage (RES)
Low Voltage Reset
I/O Port Sink Current
IOH I/O Port Source Current
RPH Pull-high Resistance
EAD A/D Conversion Error
Test Conditions
VDD Conditions
3V ¾
5V ¾
3V ¾
5V ¾
3V ¾
5V ¾
¾¾
3V VOL=0.1VDD
5V VOL=0.1VDD
3V VOH=0.9VDD
5V VOH=0.9VDD
3V ¾
5V ¾
¾¾
Min. Typ. Max. Unit
0.7VDD ¾ VDD V
0.7VDD ¾ VDD V
0 ¾ 0.4VDD V
0 ¾ 0.4VDD V
0.9VDD ¾ VDD V
0.9VDD ¾ VDD V
2.7 3 3.3 V
4 8 ¾ mA
10 20 ¾ mA
-2 -4 ¾ mA
-5 -10 ¾ mA
40 60 80 kW
10 30 50 kW
¾ ±0.5 ±1 LSB
A.C. Characteristics
Symbol
Parameter
fSYS1
System Clock (Crystal OSC)
fSYS2
System Clock (RC OSC)
fTIMER Timer I/P Frequency (TMR)
tAD A/D Clock Period
tADC A/D Conversion Time
tWDTOSC Watchdog Oscillator
tRES External Reset Low Pulse Width
tSST System Start-up Timer Period
tINT Interrupt Pulse Width
tIIC I2C BUS Clock Period
tOPT Option Load Time During Reset
Note: *tSYS=1/fSYS
Test Conditions
VDD Conditions
Min.
3V ¾
400
5V ¾
400
3V ¾
400
5V ¾
400
3V ¾
0
5V ¾
0
5V ¾
1
¾¾
¾
3V ¾
43
5V ¾
35
¾¾
1
¾ Wake-up from HALT
¾
¾¾
1
Connect to external
¾ pull-high resistor 2kW
64
3V System power on, WDT
time-out at normal mode,
5V RES is reset
45
35
Typ.
¾
¾
¾
¾
¾
¾
¾
76
86
65
¾
1024
¾
¾
90
70
Ta=25°C
Max. Unit
4000
8000
4000
8000
4000
8000
¾
¾
168
130
¾
¾
¾
kHz
kHz
kHz
kHz
kHz
kHz
ms
tAD
ms
ms
ms
*tSYS
ms
¾ *tSYS
180 ms
140 ms
Rev. 1.10
5 October 2, 2002
5 Page 
HT46R22/HT46C22
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. In-
terrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications.
If only one stack is left and enabling the interrupt is not
well controlled, the original control sequence will be dam-
aged once the ²CALL² operates in the interrupt subrou-
tine.
Oscillator configuration
There are two oscillator circuits in the microcontroller.
V DD
O SC1
O SC1
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O SC2
fS Y S /4
O SC2
N M O S O p e n D r a in
C r y s ta l O s c illa to r
R C O s c illa to r
System oscillator
Both are designed for system clocks, namely the RC os-
cillator and the Crystal oscillator, which are determined
by the options. No matter what oscillator type is se-
lected, the signal provides the system clock. The HALT
mode stops the system oscillator and ignores an exter-
nal signal to conserve power.
If an RC oscillator is used, an external resistor between
OSC1 and VSS is required and the resistance must
range from 30kW to 750kW. The system clock, divided
by 4, is available on OSC2, which can be used to syn-
chronize external logic. The RC oscillator provides the
most cost effective solution. However, the frequency of
oscillation may vary with VDD, temperatures and the
chip itself due to process variations. It is, therefore, not
suitable for timing sensitive operations where an accu-
rate oscillator frequency is desired.
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift required for the oscillator, and no other external
components are required. Instead of a crystal, a resona-
tor can also be connected between OSC1 and OSC2 to
get a frequency reference, but two external capacitors in
OSC1 and OSC2 are required (If the oscillating fre-
quency is less than 1MHz).
The WDT oscillator is a free running on-chip RC oscillator,
and no external components are required. Even if the sys-
tem enters the power down mode, the system clock is
stopped, but the WDT oscillator still works with a period of
approximately 65ms/5V. The WDT oscillator can be dis-
abled by options to conserve power.
Watchdog Timer - WDT
The clock source of the WDT is implemented by an dedi-
cated RC oscillator (WDT oscillator) or instruction clock
(system clock divided by 4) decided by options. This
timer is designed to prevent a software malfunction or
sequence jumping to an unknown location with unpre-
dictable results. The watchdog Timer can be disabled by
an option. If the watchdog Timer is disabled, all the exe-
cutions related to the WDT result in no operation.
Once an internal WDT oscillator (RC oscillator with pe-
riod 65ms normally) is selected, it is divided by 212~215
(by option to get the WDT time-out period). The mini-
mum period of WDT time-out period is about
300ms~600ms. This time-out period may vary with tem-
perature, VDD and process variations. By selection the
WDT options, longer time-out periods can be realized. If
the WDT time-out is selected 215, the maximum time-out
period is divided by 215~216about 2.3s~4.7s.
If the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operate in the same
manner except that in the halt state the WDT may stop
counting and lose its protecting purpose. In this situation
the logic can only be restarted by external logic. If the
device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
The WDT overflow under normal operation will initialize
²chip reset² and set the status bit TO. Whereas in the
HALT mode, the overflow will initialize a ²warm reset² only
the PC and SP are reset to 0. To clear the contents of
WDT, three methods are adopted; external reset (a low
level to RES), software instructions, or a HALT instruction.
The software instructions include CLR WDT and the other
set - CLR WDT1 and CLR WDT2. Of these two types of
instruction, only one can be active depending on the op-
S y s te m C lo c k /4
W DT
O SC
O p tio n fS
S e le c t
D iv id e r
fS /2 8
W D T P r e s c a le r
M a s k O p tio n
CK T
R
W D T C le a r
Watchdog Timer
CK T
R
T im e - o u t R e s e t
fS /2 1 5 ~ fS /2 1 6
fS /2 1 4 ~ fS /2 1 5
fS /2 1 3 ~ fS /2 1 4
fS /2 1 2 ~ fS /2 1 3
Rev. 1.10
11 October 2, 2002
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 46R22.PDF ] | |
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