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PDF UC284xA Data sheet ( Hoja de datos )

Número de pieza UC284xA
Descripción HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER
Fabricantes STMicroelectronics 
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No Preview Available ! UC284xA Hoja de datos, Descripción, Manual

UC284XA
UC384XA
HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER
NOT FOR NEW DESIGN
1 FEATURES
TRIMMED OSCILLATOR DISCHARGE
CURRENT
CURRENT MODE OPERATION TO 500kHz
AUTOMATIC FEED FORWARD
COMPENSATION
LATCHING PWM FOR CYCLE-BY-CYCLE
www.DataShCeUetR4UR.cEoNmT LIMITING
INTERNALLY TRIMMED REFERENCE WITH
UNDERVOLTAGE LOCKOUT
HIGH CURRENT TOTEM POLE OUTPUT
UNDERVOLTAGE LOCKOUT WITH
HYSTERESIS
LOW START-UP CURRENT (< 0.5mA)
DOUBLE PULSE SUPPRESSION
2 DESCRIPTION
The UC384xA family of control ICs provides the
necessary features to implement off-line or DC to
DC fixed frequency current mode control schemes
with a minimal external parts count. Internally im-
plemented circuits include a trimmed oscillator for
precise DUTY CYCLE CONTROL under voltage
lockout featuring start-up current less than 0.5mA,
a precision reference trimmed for accuracy at the
error amp input, logic to insure latched operation,
a PWM comparator which also provides current
limit control, and a totem pole output stage de-
signed to source or sink high peak current. The
output stage, suitable for driving N-Channel MOS-
FETs, is low in the off-state.
Figure 1. Package
DIP-8
Table 1. Order Codes
Part Number
UC2842AD1; UC3842AD1;
UC2843AD1; UC3843AD1;
UC2844AD1; UC3844AD1;
UC2845AD1; UC3845AD1
UC2842AN; UC3842AN;
UC2843AN; UC3843AN;
UC2844AN; UC3844AN;
UC2845AN; UC3845AN
SO-8
Package
SO-8
DIP-8
Differences between members of this family are
the under-voltage lockout thresholds and maxi-
mum duty cycle ranges. The UC3842A and
UC3844A have UVLO thresholds of 16V (on) and
10V (off), ideally suited off-line applications The
corresponding thresholds for the UC3843A and
UC3845A are 8.5 V and 7.9V. The UC3842A and
UC3843A can operate to duty cycles approaching
100%. A range of the zero to < 50 % is obtained by
the UC3844A and UC3845A by the addition of an
internal toggle flip flop which blanks the output off
every other clock cycle.
Figure 2. Block Diagram (toggle flip flop used only in UC3844A and UC3845A)
7
Vi
5
GROUND
4
RT/CT
VFB
COMP
CURRENT
SENSE
2
1
3
34V UVLO
S/R
5V
REF
2.50V
VREF GOOD
LOGIC
INTERNAL
BIAS
OSC
ERROR AMP.
+
-
2R
R
T
S
R
1V
CURRENT
SENSE
COMPARATOR
PWM
LATCH
8 VREF
5V 50mA
6
OUTPUT
D95IN331
May 2004
REV. 5
1/16

1 page




UC284xA pdf
UC384XA - UC284XA
Figure 4. Open Loop Test Circuit.
4.7K
ERROR AMP.
ADJUST
4.7K
2N2222
100K
1K
ISENSE
ADJUST
5K
RT
COMP
VFB
ISENSE
RT/CT
VREF
8
1
2
3
4
0.1µF
7
Vi
0.1µF
OUTPUT
6
GROUND
5
A
1W
1K
VREF
Vi
OUTPUT
www.DataSheet4U.com
D95IN343
CT
GROUND
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and
bypass capacitors should be connected close to pin 5 in a single point ground. The transistor and 5 K
potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3.
Figure 5. Oscillator Frequency vs Timing
Resistance
fo
(Hz)
D96IN362
1M
100K
10K
CT=470pF
1nF
2.2nF
4.7nF
Figure 7. Oscillator Discharge Current vs.
Temperature.
Idischg
(mA)
8.5
D95IN335
Vi=15V
VOSC=2V
8.0
7.5
1K
300
1K 3K 10K 30K RT()
Figure 6. Maximum Duty Cycle vs Timing
Resistor
fo
(Hz)
D96IN363
80
60
40
20
0
300
1K 3K 10K 30K RT()
7.0
-55 -25 0 25 50 75 100 TA(˚C)
Figure 8. Error Amp Open-Loop Gain and
Phase vs. Frequency.
(dB)
D95IN337 φ
Vi=15V
80 VO=2V to 4V 30
Gain
RL=100K
TA=25˚C
60 60
40 90
Phase
20 120
0 150
-20 180
10 100 1K 10K 100K 1M f(Hz)
5/16

5 Page





UC284xA arduino
UC384XA - UC284XA
Figure 25. External Duty Cycle Clamp and Multi Unit Synchronization.
VREF
RA
RB 5K
6
5
5K
2
www.DataSheeCt4U.com
5K
8
+
-
+
-
1
4
R
Q
S
NE555
1.44
f=
(RA + 2RB)C
Dmax =
RB
RA + 2RB
3
7
8
R
BIAS
R
4
OSC
+
+
2
-
EA
1
2R
R
5
TO ADDITIONAL
UCX84XAs
D95IN353
Figure 26. Soft-Start Circuit
8
4
1M
C
2
1
R
BIAS
R
OSC
+
+
-
EA
1mA
2R
R
5Vref
+
-
+
1V -
S
Q
R
5
D95IN354
11/16

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