PDF PLL102-109 Data sheet ( Hoja de datos )

Número de pieza	PLL102-109
Descripción	Programmable DDR Zero Delay Clock Driver
Fabricantes	PhaseLink Corporation
Logotipo
Hay una vista previa y un enlace de descarga de PLL102-109 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas
No Preview Available ! Preliminary PLL102-109 Programmable DDR Zero Delay Clock Driver FEATURES • PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz. • Distributes one clock Input to one bank of six differential outputs. • Track spread spectrum clocking for EMI reduction. • Programmable delay between CLK_INT and CLK[T/C] from –0.8ns to +3.1ns by programming CLKINT and www.DataSheet4U.FcoBmOUT skew channel, or from –1.1ns to +3.5ns if additional DDR skew channels are enabled. • Two independent programmable DDR skew chan- nels from –0.3ns to +0.4ns with step size ±100ps. • Support 2-wire I2C serial bus interface. • 2.5V Operating Voltage. • Available in 28-Pin 209mil SSOP. PIN CONFIGURATION CLKCO CLKT0 VDD CLKT1 CLKC1 GND SCLK CLK_INT N/C AVDD AGND VDD CLKT2 CLKC2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND CLKC5 CLKT5 CLKC4 CLKT4 VDD SDATA N/C FB_INT FB_OUTT ADDR_SEL CLKT3 CLKC3 GND DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purposes by strapping AVDD to ground. BLOCK DIAGRAM AVDD CLK_INT FB_INT AV DD Programmable Delay Channel (0~2.5ns) +170ps step Control Logic PLL Programmable Skew Channel -600~+800ps ±200ps step -300~+400ps ±100ps step -300~+400ps ±100ps step FB_OUTT CLKT0 CLKC0 CLKT1 CLKC1 CLKT5 CLKC5 CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 02/26/03 Page 1 1 page Preliminary PLL102-109 Programmable DDR Zero Delay Clock Driver 5. BYTE 8: Outputs Register (1=Enable, 0=Disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 www.DataSheet4U.coBmit 3 Bit 2 Bit 1 Bit 0 Name - Skew FBOUT Bit <2> Bit <1> Bit <0> Bit <3> Delay CLKINT Bit <2> Bit <1> Bit <0> Default Description 1 Reserved 0 These three bits will adjust timing of FBOUTT signal either positive 1 or negative delay up to +800ps or –600ps with ±200ps per step. 1 (see Table 1) 0 0 These four bits will program the propagation delay from CLK_INT to the input of PLL within the range between 0ps and 2.5ns with 0 170ps step size. (see Table 2) 0 TABLE 2: CLK_INT Delay Programming Summary: Bit<3:0> 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 CLK_INT to CLK Delay +2,550 ps +2,380 ps +2,210 ps +2,040 ps +1,870 ps +1,700 ps +1,530 ps +1,360 ps +1,190 ps +1,020 ps +850 ps +680 ps +510 ps +340 ps +170 ps Default 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 02/26/03 Page 5 5 Page

Páginas	Total 10 Páginas
PDF Descargar	[ Datasheet PLL102-109.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
PLL102-10	Low Skew Output Buffer	PhaseLink Corporation
PLL102-108	Programmable DDR Zero Delay Clock Driver	PhaseLink Corporation
PLL102-109	Programmable DDR Zero Delay Clock Driver	PhaseLink Corporation

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar