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PDF CY62167EV18 Data sheet ( Hoja de datos )
| Número de pieza | CY62167EV18 | |
| Descripción | 16-Mbit (1M x 16) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY62167EV18 MoBL®
16-Mbit (1M x 16) Static RAM
Features
■ Very high speed: 55 ns
■ Wide voltage range: 1.65V – 2.25V
■ Ultra low standby power
❐ Typical standby current: 1.5 µA
❐ Maximum standby current: 12 µA
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■ Ultra low active power
❐ Typical active current: 2.2 mA @ f = 1 MHz
■ Easy memory expansion with CE1, CE2, and OE features
■ Automatic power down when deselected
■ CMOS for optimum speed and power
■ Offered in Pb-free 48-ball VFBGA packages
Functional Description
The CY62167EV18 is a high performance CMOS static RAM
organized as 1M words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that reduces power consumption
Logic Block Diagram
by 99% when addresses are not toggling. Place the device into
standby mode when deselected (CE1 HIGH or CE2 LOW or both
BHE and BLE are HIGH). The input and output pins (IO0 through
IO15) are placed in a high impedance state when: the device is
deselected (CE1HIGH or CE2 LOW); outputs are disabled (OE
HIGH); both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH); and a write operation is in progress (CE1
LOW, CE2 HIGH and WE LOW).
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from IO pins (IO0 through IO7) is written
into the location specified on the address pins (A0 through A19).
If Byte High Enable (BHE) is LOW, then data from IO pins (IO8
through IO15) is written into the location specified on the address
pins (A0 through A19).
To read from the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from
memory appears on IO8 to IO15. See the Truth Table on page 9
for a complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Power Down
Circuit
DATA IN DRIVERS
A10
A9
A
A
A
8
7
6
1M × 16
A 5 RAM ARRAY
A4
A3
A2
A
A
1
0
COLUMN DECODER
CE2
CE1
BHE
BLE
IO0–IO7
IO8–IO15
BHE
WE
OE
BLE
CE2
CE1
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-05447 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 16, 2007
1 page  
Switching Characteristics
Over the Operating Range[12, 13]
Parameter
Description
Read Cycle
tRC Read Cycle Time
tAA Address to Data Valid
tOHA
Data Hold from Address Change
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tDOE
tLZOE
tHZOE
tLZCE
tHZCE
CE1 LOW and CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[14]
OE HIGH to High-Z[14, 15]
CE1 LOW and CE2 HIGH to Low-Z[14]
CE1 HIGH and CE2 LOW to High-Z[14, 15]
tPU CE1 LOW and CE2 HIGH to Power Up
tPD CE1 HIGH and CE2 LOW to Power Down
tDBE
BLE/BHE LOW to Data Valid
tLZBE
BLE/BHE LOW to Low-Z[14]
tHZBE
BLE/BHE HIGH to High-Z[14, 15]
Write Cycle[16]
tWC
tSCE
tAW
tHA
tSA
tPWE
tBW
tSD
tHD
tHZWE
tLZWE
Write Cycle Time
CE1 LOW and CE2 HIGH to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z[14, 15]
WE HIGH to Low-Z[14]
CY62167EV18 MoBL®
55 ns
Min Max
55
55
10
55
25
5
18
10
18
0
55
55
10
18
55
40
40
0
0
40
40
25
0
20
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
12.
Test
of 0
conditions
to VCC(typ),
for all parameters other than tri-state parameters are
and output loading of the specified IOL/IOH as shown
based on signal transition time of 1V/ns, timing
in AC Test Loads and Waveforms on page 4.
reference
levels
of
VCC(typ)/2,
input
pulse
levels
13. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
14.
At any given
device.
temperature
and
voltage
condition,
tHZCE
is
less
than
tLZCE,
tHZBE
is
less
than
tLZBE,
tHZOE
is
less
than
tLZOE,
and
tHZWE
is
less
than
tLZWE
for
any
given
15. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the output enters a high impedance state.
16.
The
any
internal
of these
memory write time is
signals can terminate
adewfriniteedbybygothinegoIvNeArlCaTpIoVfEW. TEh,eCdEa1ta=inVpILu,t
BseHtEupaanndd/ohroBldLEtim=inVgILm, aunstdbCeEre2f=erVenIHc.eAdlltositghneaelsdgmeuosfttbhee
ACTIVE to initiate a write and
signal that terminates the write.
Document #: 38-05447 Rev. *E
Page 5 of 12
5 Page 
CY62167EV18 MoBL®
Package Diagram
TOP VIEW
Figure 9. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150
www.DataSheet4U.com
A1 CORNER
12 3 4 5 6
A
B
C
D
E
F
G
H
BOTTOM VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
Ø0.30±0.05(48X)
6 54 3 2 1
A
B
C
D
E
F
G
H
A
B
6.00±0.10
A 1.875
0.75
3.75
B
0.15(4X)
6.00±0.10
SEATING PLANE
C
51-85150-*D
Document #: 38-05447 Rev. *E
Page 11 of 12
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| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet CY62167EV18.PDF ] | |
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