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부품번호 | TTS3816B4E 기능 |
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기능 | 2M x 16Bit x 4 Banks synchronous DRAM | ||
제조업체 | TwinMOS | ||
로고 | |||
M.tec
2M x 16Bit x 4 Banks synchronous DRAM
TTS3816B4E
GENERAL DESCRIPTION
The TTS3816B4E is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 8 x 1,048,576 words by 16 bits,
fabricated with M’tec high performance CMOS technology. Synchronous design allows precise cycle control with the use of
system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and
www.DataShpereot4gUra.cmommable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system
applications.
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four-banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
ORDERING INFORMATION
Part No.
TTS3816B4E-7
TTS3816B4E-6
TTS3816B4E-6A
TTS3816B4E-6B
TTS3816B4E-6C
TTS3816B4E-6D
TTS3816B4E-6E
Max Freq.
100MHz 2-2-2
133MHz 3-3-3
100MHz 2-3-3
133MHz 2-3-2
133MHz 2-2-2
150MHz 3-3-3
166MHz 3-3-3
Interface
Package
LVTTL
54
TSOP(II)
Revision_1.1
1 TwinMOS Technologies Inc. Sep. 2000
M.tec
BLOCK DIAGRAM
TTS3816B4E
www.DataSheet4U.com
Bank Select
Data Input
ADD
Address
Buffer
/CS
/ RAS
/ CAS
/ WE
CLK
CKE
Commend
Decoder
&
Clock
Buffer
Row Decoder
&
Refresh Counter
Column Buffer
Programming
Register
2MX16
2MX16
2MX16
2MX16
Column Decoder
Latency &
Burst Length
Output Buffer
DQ
Revision_1.1
4 TwinMOS Technologies Inc. Sep. 2000
4페이지 M.tec
TTS3816B4E
AC CHARACTERISTICS AND OPERATING
(Vcc=3.3V±0.3V, Ta=0° to 70°C)
Parameter
-7 -6 -6A -6B -6C -6D -6E
Symbol
Unit
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Row active to row active delay
tRRD
20 15 20 14 14 14 12 ns
/RAS to /RAS delay
tRCD
20 20 30 20 15 20 18 ns
Row pre-charge time
www.DataSheReto4wU.acocmtive time
tRP
tRAS
20 20 30 15 15 20 18 ns
48 100K 45 100K 48 100K 45 100K 45 100K 45 100K 42 100K ns
Row cycle time
tRC 70 67.5 70 63 63 63 60 ns
Col. Address to col. Address delay tCCD
1 1 1 1 1 1 1 CLK
Write Recovery Time
tWR 20 15 20 14 14 13 12 ns
CLK Cycle Time
CL=2 10 1000 10 1000 10 1000 7.5 1000 7.5 1000 -
-
tCK ns
CL=3 8 1000 7.5 1000 8 1000 7.5 1000 7.5 1000 6.5 1000 6 1000
CLK High Level width
tCH
3 2.5 3 2.5 2.5 2
2 ns
CLK Low Level width
tCL
3 2.5 3 2.5 2.5 2
2 ns
Access Time from CLK
CL=2
6
6
8 5.4 5.4 -
-
tAC ns
CL=3 6 5.4 6 5.4 5.4 5.4 5
Output Data Hold Time
tOH 3 2.7 3 2.7 2.7 2.5 2 ns
Data-in Set-up Time
tDS 2 1.5 2 1.5 1.5 1.5 1.5 ns
Data-in Hold Time
tDH 1 1 1 1 1 1 1 ns
Address Set-up Time
tAS 2 1.5 2 1.5 1.5 1.5 1.5 ns
Address Hold Time
tAH 1 1 1 1 1 1 1 ns
CKE Set-up Time
tCKS 2 1.5 2 1.5 1.5 1.5 1.5 ns
CKE Hold Time
tCKH
1 1 1 1 1 1 1 ns
Command Set-up Time
tCMS
2 1.5 2 1.5 1.5 1.5 1.5 ns
Command Hold Time
tCMH
1 1 1 1 1 1 1 ns
Refresh Time
tREF 64 64 64 64 64 64 64 ms
Mode register Set Cycle Time
tRSC
20 15 20 14 14 12 12 ns
Revision_1.1
7 TwinMOS Technologies Inc. Sep. 2000
7페이지 | |||
구 성 | 총 8 페이지수 | ||
다운로드 | [ TTS3816B4E.PDF 데이터시트 ] |
당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는 |
구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
TTS3816B4E | 2M x 16Bit x 4 Banks synchronous DRAM | TwinMOS |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |