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PDF W196 Data sheet ( Hoja de datos )
| Número de pieza | W196 | |
| Descripción | Spread Spectrum FTG | |
| Fabricantes | SpectraLinear | |
| Logotipo |  |
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W196
Spread Spectrum FTG for 440BX and VIA Apollo Pro-133
1W196
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
www.DataShe•etS4Uys.ctoemm frequency synthesizer for 440BX, 440ZX, and
VIA Apollo Pro-133
• I2C programmable to 155 MHz (32 selectable
frequencies)
• Two skew-controlled copies of CPU output
• Seven copies of PCI output (synchronous w/CPU
output)
• One copy of 14.31818-MHz IOAPIC output
• One copy of 48-MHz USB output
• Selectable 24-/48-MHz clock is determined by resistor
straps on power up
• One high-drive output buffer that produces a copy of
the 14.318-MHz reference
• Isolated core VDD pin for noise reduction
Key Specifications
Supply Voltages:........................................VDDQ3 = 3.3V±5%
...............................................................................................
VDDQ2 = 2.5V±5%
CPU Cycle to Cycle Jitter: ......................................... 250 ps
CPU, PCI Output Edge Rate: t1 V/ns
CPU0:1 Output Skew: ................................................ 175 ps
PCI_F, PCI1:6 Output Skew: ...................................... 500 ps
CPU to PCI Skew: ........................1.5 to 4.0 ns (CPU Leads)
REF2X/SEL48#, SCLOCK, SDATA: ...............250-k: pull-up
FS1: ........................................................... 250-k: pull-down
FS0: .................................................. No pull-up or pull-down
Note: Internal pull-up or pull-down resistors should not be
relied upon for setting I/O pins HIGH or LOW.
Table 1. Pin Selectable Frequency
FS1 FS0 CPU(0:1) PCI
1 1 133.3 MHz 33.3 MHz
1
0
105 MHz
35 MHz
0
1
100 MHz
33.3 MHz
0 0 66.8 MHz 33.3 MHz
Rev 1.0, November 28, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555 Fax:(408) 855-0550
Page 1 of 11
www.SpectraLinear.com
1 page  
W196
Serial Data Interface
The W196 features a two-pin, serial data interface that can be
used to configure internal register settings that control
particular device functions. Upon power-up, the W196
initializes with default register settings. Therefore, the use of
this serial data interface is optional. The serial interface is
write-only (to the clock chip) and is the dedicated function of
device pins SDATA and SCLOCK. In motherboard applica-
tions, SDATA and SCLOCK are typically driven by two logic
outputs of the chipset. Clock device register changes are
normally made upon system initialization, if required. The
interface can also be used during system operation for power
management functions. Table 2 summarizes the control
functions of the serial data interface.
Operation
Data is written to the W196 in ten bytes of eight bits each.
Bytes are written in the order shown in Table 3.
www.DataShTeaebt4lUe.c2o.mSerial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output Disable Any individual clock output(s) can be disabled.
Disabled outputs are actively held LOW.
Unused outputs are disabled to reduce EMI and
system power. Examples are clock outputs to
unused PCI slots.
CPU Clock Frequency
Selection
Provides CPU/PCI frequency selections beyond
the selections that are provided by the FS0:1 pins.
Frequency is changed in a smooth and controlled
fashion.
For alternate microprocessors and power
management options. Smooth frequency
transition allows CPU frequency change under
normal system operation.
Output Three-state Puts all clock outputs into a high-impedance state. Production PCB testing.
Test Mode
All clock outputs toggle in relation to X1 input,
internal PLL is bypassed. Refer to Table 4.
Production PCB testing.
(Reserved)
Reserved function for future device revision or
production device testing.
No user application. Register bit must be written
as 0.
Table 3. Byte Writing Sequence
Byte
Sequence
1
Byte Name
Slave Address
Bit Sequence
11010010
2 Command Don’t Care
Code
3
Byte Count
Don’t Care
4
Data Byte 0
Don’t Care
5 Data Byte 1
6 Data Byte 2
7
Data Byte 3
Refer to Table 4
8 Data Byte 4
9 Data Byte 5
10 Data Byte 6
Byte Description
Commands the W196 to accept the bits in Data Bytes 3–6 for internal
register configuration. Since other devices may exist on the same
common serial data bus, it is necessary to have a specific slave address
for each potential receiver. The slave receiver address for the W196 is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
Unused by the W196, therefore bit values are ignored (“don’t care”). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Command Code Byte is part of the standard serial
communication protocol and may be used when writing to another
addressed slave receiver on the serial data bus.
Unused by the W196, therefore bit values are ignored (“don’t care”). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Byte Count Byte is part of the standard serial communi-
cation protocol and may be used when writing to another addressed slave
receiver on the serial data bus.
Refer to Cypress SDRAM drivers.
The data bits in these bytes set internal W196 registers that control device
operation. The data bits are only accepted when the Address Byte bit
sequence is 11010010, as noted above. For description of bit control
functions, refer to Table 4, Data Byte Serial Configuration Map.
Rev 1.0, November 28, 2006
Page 5 of 11
5 Page 
W196
48-MHZ and 24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
fD
m/n
tR
tF
www.DataSheteDt4U.com
fST
Zo
Deviation from 48 MHz
PLL Ratio
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Frequency Stabilization
from Power-up (cold start)
AC Output Impedance
(48.008 – 48)/48
(14.31818 MHz x 57/17 = 48.008 MHz)
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to
frequency stabilization.
Average value during switching transition. Used
for determining series termination value.
Min. Typ. Max.
48.008
24.004
+167
57/17, 57/34
0.5 2
0.5 2
45 55
3
25
Unit
MHz
ppm
V/ns
V/ns
%
ms
:
Ordering Information
Ordering Code
W196
Package
Name
G
Package Type
28-pin SOIC (300 mils)
Package Diagram
DIMENSIONS IN INCHES[MM]
PART #
S28.4 STANDARD PKG.
SZ28.4 LEAD FREE PKG.
14
MIN.
MAX. 28-Lead (400-Mil) Molded SOIC S28
DETAIL A
PIN 1 ID
EXTERNAL LEAD DESIGN
1
15
.720[18.288]
.730[18.542]
.395[10.033]
.405[10.287]
.530[13.462]
.545[13.843]
28
SEATING PLANE
.013[0.330]
.019[0.482]
OPTION 1
.026[0.660]
.032[0.812]
.015[0.381]
.020[0.508]
OPTION 2
.090[2.286]
.109[2.768]
.050[1.270]
TYP.
A
.002[0.050]
.014[0.355]
0.004[0.102]
.015[0.381]
.050[1.270]
.007[0.177]
.013[0.330]
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir-
cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in
normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica-
tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional
processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any
circuitry or specification without notice.
Rev 1.0, November 28, 2006
Page 11 of 11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet W196.PDF ] | |
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