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27SF512 데이터시트 PDF




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기능 SST27SF512
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27SF512 데이터시트, 핀배열, 회로
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit (x8)
Many-Time Programmable Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
SST27SF256 / 512 / 010 / 0205.0V-Read 256Kb / 512Kb / 1Mb / 2Mb (x8) MTP flash memories
FEATURES:
Data Sheet
• Organized as 32K x8 / 64K x8 / 128K x8 / 256K x8
• 4.5-5.5V Read Operation
• Superior Reliability
– Endurance: At least 1000 Cycles
– Greater than 100 years Data Retention
Low Power Consumption
Active Current: 20 mA (typical)
Standby Current: 10 µA (typical)
www.DataSheet4UF.caosmt Read Access Time
70 ns
90 ns
Fast Byte-Program Operation
Byte-Program Time: 20 µs (typical)
Chip Program Time:
0.7 seconds (typical) for SST27SF256
1.4 seconds (typical) for SST27SF512
2.8 seconds (typical) for SST27SF010
5.6 seconds (typical) for SST27SF020
Electrical Erase Using Programmer
Does not require UV source
Chip-Erase Time: 100 ms (typical)
TTL I/O Compatibility
JEDEC Standard Byte-wide EPROM Pinouts
Packages Available
32-pin PLCC
32-pin TSOP (8mm x 14mm)
28-pin PDIP for SST27SF256/512
32-pin PDIP for SST27SF010/020
PRODUCT DESCRIPTION
The SST27SF256/512/010/020 are a 32K x8 / 64K x8 /
128K x8 / 256K x8 CMOS, Many-Time Programmable
(MTP) low cost flash, manufactured with SSTs proprietary,
high performance SuperFlash technology. The split-gate
cell design and thick oxide tunneling injector attain better
reliability and manufacturability compared with alternate
approaches. These MTP devices can be electrically erased
and programmed at least 1000 times using an external pro-
grammer with a 12 volt power supply. They have to be
erased prior to programming. These devices conform to
JEDEC standard pinouts for byte-wide memories.
Featuring high performance Byte-Program, the
SST27SF256/512/010/020 provide a Byte-Program time of
20 µs. Designed, manufactured, and tested for a wide
spectrum of applications, these devices are offered with an
endurance of at least 1000 cycles. Data retention is rated at
greater than 100 years.
The SST27SF256/512/010/020 are suited for applications
that require infrequent writes and low power nonvolatile
storage. These devices will improve flexibility, efficiency,
and performance while matching the low cost in nonvolatile
applications that currently use UV-EPROMs, OTPs, and
mask ROMs.
To meet surface mount and conventional through hole
requirements, the SST27SF256/512 are offered in 32-pin
PLCC, 32-pin TSOP, and 28-pin PDIP packages. The
SST27SF010/020 are offered in 32-pin PDIP, 32-pin PLCC
and 32-pin TSOP packages. See Figures 1, 2, and 3 for
pinouts.
©2001 Silicon Storage Technology, Inc.
S71152-02-000 5/01
502
1
Device Operation
The SST27SF256/512/010/020 are a low cost flash solu-
tion that can be used to replace existing UV-EPROM, OTP,
and mask ROM sockets. These devices are functionally
(read and program) and pin compatible with industry stan-
dard EPROM products. In addition to EPROM functionality,
these devices also support electrical erase operation via an
external programmer. They do not require a UV source to
erase, and therefore the packages do not have a window.
Read
The Read operation of the SST27SF256/512/010/020 is
controlled by CE# and OE#. Both CE# and OE# have to be
low for the system to obtain data from the outputs. Once
the address is stable, the address access time is equal to
the delay from CE# to output (TCE). Data is available at the
output after a delay of TOE from the falling edge of OE#,
assuming that CE# pin has been low and the addresses
have been stable for at least TCE - TOE. When the CE# pin
is high, the chip is deselected and a typical standby current
of 10 µA is consumed. OE# is the output control and is
used to gate data from the output pins. The data bus is in
high impedance state when either CE# or OE# is high.
Byte-Program Operation
The SST27SF256/512/010/020 are programmed by using
an external programmer. The programming mode for
SST27SF256/010/020 is activated by asserting 12V (±5%)
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MTP is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.




27SF512 pdf, 반도체, 판매, 대치품
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
Data Sheet
www.DataSheet4U.com
SST27SF020 SST27SF010 SST27SF512 SST27SF256
SST27SF256 SST27SF512 SST27SF010 SST27SF020
4 3 2 1 32 31 30
A7 A7 A6 A6 5
29 A8
A8 A14 A14
A6 A6 A5 A5 6
28 A9
A9 A13 A13
A5 A5 A4 A4 7
27 A11
A11 A8
A8
A4
A4
A3
A3 8
32-pin PLCC
26 NC
NC A9 A9
A3
A2
A3
A2
A2 A2 9
A1 A1 10
Top View
25 OE#
24 A10
OE#/VPP A11
A10 OE#
A11
OE#
A1 A1 A0 A0 11
23 CE#
CE# A10 A10
A0 A0 NC NC 12
22 DQ7
DQ7 CE# CE#
DQ0
DQ0
DQ0
DQ0
13 21
14 15 16 17 18 19 20
DQ6
DQ6
DQ7
DQ7
502 ILL F02c.2
FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN PLCC
©2001 Silicon Storage Technology, Inc.
4
S71152-02-000 5/01 502

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27SF512 전자부품, 판매, 대치품
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
Data Sheet
TABLE 3: OPERATION MODES SELECTION FOR SST27SF256
Mode
Read
Output Disable
Byte-Program
Standby
Chip-Erase
Program/Erase Inhibit
Product Identification
www.DataSheet4U.com
CE#
VIL
VIL
VIL
VIH
VIL
VIH
VIL
OE#
VIL
VIH
VIH
X
VIH
X
VIL
VPP
VDD or VSS
VDD or VSS
VPPH
VDD or VSS
VPPH
VPPH
VDD or VSS
Note: X = VIL or VIH
VPPH = 12V±5%, VH = 12V±5%
A9 DQ
AIN DOUT
X High Z
AIN DIN
X High Z
VH High Z
X High Z
VH Manufacturers ID (BFH)
Device ID (A3H)
Address
AIN
X
AIN
X
X
X
A14 - A1 = VIL, A0 = VIL
A14 - A1 = VIL, A0 = VIH
T3.1 502
TABLE 4: OPERATION MODES SELECTION FOR SST27SF512
Mode
Read
Output Disable
Program
Standby
Chip-Erase
Program/Erase Inhibit
Product Identification
CE#
VIL
VIL
VIL
VIH
VIL
VIH
VIL
Note: X = VIL or VIH
VPPH = 12V±5%, VH = 12V±5%
OE#/VPP
VIL
VIH
VPPH
X
VPPH
VPPH
VIL
A9 DQ
AIN DOUT
X High Z
AIN DIN
X High Z
VH High Z
X High Z
VH Manufacturers ID (BFH)
Device ID (A4H)
Address
AIN
X
AIN
X
X
X
A15 - A1 = VIL, A0 = VIL
A15 - A1 = VIL, A0 = VIH
T4.1 502
TABLE 5: OPERATION MODES SELECTION FOR SST27SF010/020
Mode
Read
Output Disable
Program
Standby
Chip-Erase
Program/Erase Inhibit
Product Identification
CE#
VIL
VIL
VIL
VIH
VIL
VIH
VIL
OE#
VIL
VIH
VIH
X
VIH
X
VIL
PGM#
X
X
VIL
X
VIL
X
X
A9 VPP
AIN VDD or VSS
X VDD or VSS
AIN VPPH
X VDD or VSS
VH VPPH
X VPPH
VH VDD or VSS
DQ
DOUT
High Z
DIN
High Z
High Z
High Z
Manufacturers ID (BFH)
Device ID1
1. Device ID = A5H for SST27SF010 and A6H for SST27SF020
2. AMS = Most significant address
AMS = A16 for SST27SF010 and A17 for SST27SF020
Note: X = VIL or VIH
VPPH = 12V±5%, VH = 12V±5%
Address
AIN
AIN
AIN
X
X
X
AMS2 - A1 = VIL, A0 = VIL
AMS2 - A1 = VIL, A0 = VIH
T5.1 502
©2001 Silicon Storage Technology, Inc.
7
S71152-02-000 5/01 502

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