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W79L632A 데이터시트, 핀배열, 회로
W79E632A/W79L632A Data Sheet
8-BIT MICROCONTROLLER
Table of Contents-
1.
2.
3.
4.
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5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
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20.
21.
GENERAL DESCRIPTION .................................................................................................................... 2
FEATURES............................................................................................................................................ 2
PIN CONFIGURATIONS ....................................................................................................................... 3
PIN DESCRIPTION ............................................................................................................................... 4
FUNCTIONAL DESCRIPTION .............................................................................................................. 5
MEMORY ORGANIZATION .................................................................................................................. 7
INSTRUCTION .................................................................................................................................... 26
7.1 Instruction Timing .......................................................................................................... 26
POWER MANAGEMENT..................................................................................................................... 32
INTERRUPTS...................................................................................................................................... 36
PROGRAMMABLE TIMERS/COUNTERS .......................................................................................... 38
10.1 Timer/Counters 0 & 1..................................................................................................... 38
10.2 Timer/Counter 2 ............................................................................................................. 41
10.3 Pulse Width Modulated Outputs (PWM)........................................................................ 45
10.4 Watchdog Timer ............................................................................................................ 48
SERIAL PORT ..................................................................................................................................... 52
11.1 Framing Error Detection ................................................................................................ 57
11.2 Multiprocessor Communications ................................................................................... 57
TIMED ACCESS PROTECTION ......................................................................................................... 59
H/W REBOOT MODE (BOOT FROM 4K BYTES OF LDFLASH) ....................................................... 61
IN-SYSTEM PROGRAMMING ............................................................................................................ 62
14.1 The Loader Program Locates at LDFlash Memory ....................................................... 62
14.2 The Loader Program Locates at APFlash Memory ....................................................... 62
H/W WRITER MODE........................................................................................................................... 62
SECURITY BITS.................................................................................................................................. 63
ELECTRICAL CHARACTERISTICS.................................................................................................... 64
17.1 Absolute Maximum Ratings ........................................................................................... 64
17.2 DC Characteristics......................................................................................................... 64
17.3 A.C. Characteristics ....................................................................................................... 66
TYPICAL APPLICATION CIRCUITS ................................................................................................... 70
PACKAGE DIMENSIONS.................................................................................................................... 71
APPLICATION NOTE .......................................................................................................................... 72
REVISION HISTORY........................................................................................................................... 77
Publication Release Date: February 1, 2007
- 1 - Revision A6




W79L632A pdf, 반도체, 판매, 대치품
W79E632A/W79L632A
4. PIN DESCRIPTION
SYMBOL TYPE
DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of
external ROM. It should be kept high to access internal ROM. The ROM
EA I address and data will not be present on the bus if EA pin is high and the
program counter is within 128 KB area. Otherwise they will be present on the
bus.
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PSEN
PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the
O Port 0 address/data bus during fetch and MOVC operations. When internal
ROM access is performed, no PSEN strobe signal outputs from this pin.
ALE
O
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
separates the address from the data on Port 0.
RST
I
RESET: A high on this pin for two machine cycles while the oscillator is running
resets the device.
XTAL1
I
CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an
external clock.
XTAL2
O CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.
VSS I GROUND: Ground potential
VDD I POWER SUPPLY: Supply voltage for operation.
PORT 0: Port 0 is an open-drain bi-directional I/O port. This port also provides a
P0.0 P0.7 I/O multiplexed low order address/data bus during accesses to external memory.
Port 0 has internal pull-up resisters enabled by software.
PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have
alternate functions which are described below:
P1.0 P1.7 I/O T2(P1.0): Timer/Counter 2 external count input
T2EX(P1.1): Timer/Counter 2 Reload/Capture/Direction control
P2.0 P2.7
I/O
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits for accesses to external memory.
PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. All bits have
alternate functions, which are described below:
RXD(P3.0) : Serial Port 0 input
TXD(P3.1) : Serial Port 0 output
INT0 (P3.2) : External Interrupt 0
P3.0 P3.7 I/O INT1(P3.3) : External Interrupt 1
T0(P3.4) : Timer 0 External Input
T1(P3.5) : Timer 1 External Input
WR (P3.6) : External Data Memory Write Strobe
RD (P3.7) : External Data Memory Read Strobe
PORT 4: Port 4 is a 4-bit bi-directional I/O port. The P4.3 also provides the
P4.0 P4.3 I/O alternate function REBOOT which is H/W reboot from LD flash.
* Note: TYPE I : input, O: output, I/O: bi-directional.
-4-

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W79L632A 전자부품, 판매, 대치품
W79E632A/W79L632A
6. MEMORY ORGANIZATION
The W79E(L)632 separates the memory into two separate sections, the Program Memory and the
Data Memory. The Program Memory is used to store the instruction op-codes, while the Data Memory
is used to store data or for memory mapped devices.
Program Memory
The Program Memory on the standard 8052 can only be addressed to 64 Kbytes long. By invoking the
banking methodology, W79E(L)632 can extend to two 64KB flash EPROM banks, APFlash0 and
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There are on-chip ROM
are fetched for execution
banks which can be used
from this memory area. The
similarly to that of the 8052. All
MOVC instruction can also access
this memory region. There is an auxiliary 4KB Flash EPROM bank (LDFlash) resided user loader
program for In-System Programming (ISP). Both APFlashs allow serial or parallel download according
to user loader program in LDFlash.
Data Memory
The W79E(L)632 can access up to 64Kbytes of external Data Memory. This memory region is
accessed by the MOVX instructions. Unlike the 8051 derivatives, the W79E(L)632 contains on-chip
1K bytes MOVX SRAM of Data Memory, which can only be accessed by MOVX instructions. These
1K bytes of SRAM are between address 0000H and 03FFH. Access to the on-chip MOVX SRAM is
optional under software control. When enabled by software, any MOVX instruction that uses this area
will go to the on-chip RAM. MOVX addresses greater than 03FFH automatically go to external
memory through Port 0 and 2. When disabled, the 1KB memory area is transparent to the system
memory map. Any MOVX directed to the space between 0000H and FFFFH goes to the expanded
bus on Port 0 and 2. This is the default condition. In addition, the W79E(L)632 has the standard 256
bytes of on-chip Scratchpad RAM. This can be accessed either by direct addressing or by indirect
addressing. There are also some Special Function Registers (SFRs), which can only be accessed by
direct addressing. Since the Scratchpad RAM is only 256 bytes, it can be used only when data
contents are small. In the event that larger data contents are present, two selections can be used.
One is on-chip MOVX SRAM, the other is the external Data Memory. The on-chip MOVX SRAM can
only be accessed by a MOVX instruction, the same as that for external Data Memory. However, the
on-chip RAM has the fastest access times.
Publication Release Date: February 1, 2007
- 7 - Revision A6

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W79L632A

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