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IS-80C32 데이터시트 PDF




Integrated Silicon Solution에서 제조한 전자 부품 IS-80C32은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 IS-80C32 자료 제공

부품번호 IS-80C32 기능
기능 (IS-80C32 / IS-80C52) CMOS SINGLE CHIP LOW VOLTAGE 8-BIT MICROCONTROLLER
제조업체 Integrated Silicon Solution
로고 Integrated Silicon Solution 로고


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IS-80C32 데이터시트, 핀배열, 회로
IIISSS88008CC05322C52
IS80C32
CMOS SINGLE CHIP
LOW VOLTAGE
8-BIT MICROCONTROLLER
FEATURES
• 80C51 based architecture
• 8K x 8 ROM (IS80C52 only)
• 256 x 8 RAM
www.DataSheet4TUh.croeme 16-bit Timer/Counters
• Full duplex serial channel
• Boolean processor
• Four 8-bit I/O ports, 32 I/O lines
• Memory addressing capability
– 64K ROM and 64K RAM
• Program memory lock
– Encrypted verify (32 bytes)
– Lock bits (2)
• Power save modes:
– Idle and power-down
• Eight interrupt sources
• Most instructions execute in 0.3 µs
• CMOS and TTL compatible
• Maximum speed: 40 MHz @ Vcc = 5V
• Industrial temperature available
• Packages available:
– 40-pin DIP
– 44-pin PLCC
– 44-pin PQFP
ISSISISI®®
NOVEMBER 1998
GENERAL DESCRIPTION
The ISSI IS80C52 and IS80C32 are high-performance
microcontrollers fabricated using high-density CMOS
technology. The CMOS IS80C52/32 is functionally
compatible with the industry standard 8052/32
microcontrollers.
The IS80C52/32 is designed with 8K x 8 ROM (IS80C52
only); 256 x 8 RAM; 32 programmable I/O lines; a serial
I/O port for either multiprocessor communications, I/O
expansion or full duplex UART; three 16-bit timer/counters;
an eight-source, two-priority-level, nested interrupt
structure; and an on-chip oscillator and clock circuit. The
IS80C52/32 can be expanded using standard TTL
compatible memory.
T2/P1.0
T2EX/P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RxD/P3.0
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
WR/P3.6
RD/P3.7
XTAL2
XTAL1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VCC
39 P0.0/AD0
38 P0.1/AD1
37 P0.2/AD2
36 P0.3/AD3
35 P0.4/AD4
34 P0.5/AD5
33 P0.6/AD6
32 P0.7/AD7
31 EA
30 ALE
29 PSEN
28 P2.7/A15
27 P2.6/A14
26 P2.5/A13
25 P2.4/A12
24 P2.3/A11
23 P2.2/A10
22 P2.1/A9
21 P2.0/A8
Figure 1. IS80C52/32 Pin Configuration:
40-pin PDIP
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
MC004-1D
11/19/98
1




IS-80C32 pdf, 반도체, 판매, 대치품
IS80C52
IS80C32
ISSI ®
VCC
GND
www.DataSheet4U.com
P2.0-P2.7
P2
DRIVERS
RAM ADDR
REGISTER
ADDRESS
DECODER
& 256
BYTES RAM
P2
LATCH
P0.0-P0.7
P0
DRIVERS
P0
LATCH
ADDRESS 2 LOCK BITS
DECODER
&
& 32 BYTES
8K ROM ENCRYPTION
B
REGISTER
STACK
POINT
PCON SCON
T2CON TH0
TL1 TH2
RCAP2L SBUF
TMOD TCON
TL0 TH1
TL2 RCAP2H
IE IP
INTERRUPT
SERIAL PORT
AND TIMER BLOCK
ACC
TMP2
TMP1
ALU
PSW
PSEN
ALE
RST
EA
TIMING
AND
CONTROL
OSCILLATOR
XTAL1
XTAL2
P3
LATCH
P3
DRIVERS
P1
LATCH
P1
DRIVERS
P3.0-P3.7
P1.0-P1.7
PROGRAM
ADDRESS
REGISTER
PROGRAM
COUNTER
PC
INCREMENTER
BUFFER
DPTR
Figure 4. IS80C52/32 Block Diagram
4 Integrated Silicon Solution, Inc. — 1-800-379-4774
MC004-1D
11/19/98

4페이지










IS-80C32 전자부품, 판매, 대치품
IS80C52
IS80C32
ISSI ®
OPERATING DESCRIPTION
The detail description of the IS80C52/32 included in this indirect addressing only. Figure 6 shows internal data
description are:
memory organization and SFR Memory Map.
•Memory Map and Registers
•Timer/Counters
•Serial Interface
•Interrupt System
•Other Information
www.DataSheMet4EUM.coOmRY MAP AND REGISTERS
Memory
The IS80C52/32 has separate address spaces for program
and data memory. The program and data memory can be
up to 64K bytes long. The lower 8K program memory can
reside on-chip. (IS80C52 only) Figure 5 shows a map of the
IS80C52/32 program and data memory.
The IS80C52/32 has 256 bytes of on-chip RAM, plus
numbers of special function registers. The lower 128 bytes
can be accessed either by direct addressing or by indirect
addressing. The upper 128 bytes can be accessed by
The lower 128 bytes of RAM can be divided into three
segments as listed below and shown in Figure 7.
1. Register Banks 0-3: locations 00H through 1FH
(32 bytes). The device after reset defaults to register
bank 0. To use the other register banks, the user must
select them in software. Each register bank contains
eight 1-byte registers R0-R7. Reset initializes the
stack point to location 07H, and is incremented once
to start from 08H, which is the first register of the
second register bank.
2. Bit Addressable Area: 16 bytes have been assigned
for this segment 20H-2FH. Each one of the 128 bits of
this segment can be directly addressed (0-7FH).
Each of the 16 bytes in this segment can also be
addressed as a byte.
3. Scratch Pad Area: 30H-7FH are available to the
user as data RAM. However, if the data pointer has
been initialized to this area, enough bytes should be
left aside to prevent SP data destruction.
Program Memory
(Read Only)
FFFFH:
64K
Data Memory
(Read/Write)
FFFFH:
External
EA = 0
External
1FFFH:
8K
0000
EA = 1
Internal
(IS80C52
Only)
PSEN
Internal
FFH:
00 0000
RD WR
Figure 5. IS80C52/32 Program and Data Memory Structure
Integrated Silicon Solution, Inc. — 1-800-379-4774
MC004-1D
11/19/98
7

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부품번호상세설명 및 기능제조사
IS-80C32

(IS-80C32 / IS-80C52) CMOS SINGLE CHIP LOW VOLTAGE 8-BIT MICROCONTROLLER

Integrated Silicon Solution
Integrated Silicon Solution

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