AD1839 Datasheet PDF - Analog Devices
| Part Number | AD1839 | |
| Description | 24-Bit sigma-delta Codec | |
| Manufacturers | Analog Devices | |
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2 ADC, 6 DAC,
96 kHz, 24-Bit ⌺-⌬ Codec
AD1839
FEATURES
5 V Stereo Audio System with 3.3 V Tolerant
Digital Interface
Supports up to 96 kHz Sample Rates
192 kHz Sample Rate Available on One DAC
Supports 16-/20-/24-Bit Word Lengths
Multibit ⌺-⌬ Modulators with
Perfect Differential Linearity Restoration for
www.DataSheet4U.coRmeduced Idle Tones and Noise Floor
Data Directed Scrambling DACs—Least
Sensitive to Jitter
Single-Ended Output
ADCs: –95 dB THD + N, 105 dB SNR and
Dynamic Range
DACs: –92 dB THD + N, 108 dB SNR and
Dynamic Range
On-Chip Volume Controls per Channel with
1024 Step Linear Scale
DAC and ADC Software Controllable Clickless Mutes
Digital De-emphasis Processing
Supports 256 ؋ fS, 512 ؋ fS, and 768 ؋ fS Master
Mode Clocks
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S Compatible, and DSP Serial Port Modes
TDM Interface Mode Supports 8 In/8 Out Using a
Single SHARC ® SPORT
52-Lead MQFP Plastic Package
APPLICATIONS
DVD Video and Audio Players
Home Theater Systems
Automotive Audio Systems
Audio/Visual Receivers
Digital Audio Effects Processors
PRODUCT OVERVIEW
The AD1839 is a high performance single-chip codec featuring
three stereo DACs and one stereo ADC. Each DAC comprises
a high performance digital interpolation filter, a multibit ⌺-⌬
modulator featuring Analog Devices’ patented technology, and
a continuous-time voltage out analog section. Each DAC has
independent volume control and clickless mute functions. The
ADC comprises two 24-bit conversion channels with multibit
⌺-⌬ modulators and decimation filters.
The AD1839 also contains an on-chip reference with a nominal
value of 2.25 V.
The AD1839 contains a flexible serial interface that allows
for glueless connection to a variety of DSP chips, AES/EBU
receivers, and sample rate converters. The AD1839 can be
configured in left-justified, right-justified, I2S, or DSP com-
patible serial modes. Control of the AD1839 is achieved by
means of an SPI® compatible serial port. While the AD1839
can be operated from a single 5 V supply, it also features a
separate supply pin for its digital interface that allows the device
to be interfaced to other devices using 3.3 V power supplies.
The AD1839 is available in a 52-lead MQFP package and is
specified for the industrial temperature range of –40ºC to +85ºC.
FUNCTIONAL BLOCK DIAGRAM
DVDD DVDD ODVDD ALRCLK ABCLK ASDATA CCLK CLATCH CIN COUT MCLK PD/RST M/S AVDD AVDD
AAUXDATA3
DLRCLK
DBCLK
DSDATA1
DSDATA2
DSDATA3
DAUXDATA
ADCLP
ADCLN
ADCRP
ADCRN
⌺-⌬
ADC
⌺-⌬
ADC
SERIAL DATA
I/O PORT
DIGITAL
FILTER
DIGITAL
FILTER
CONTROL PORT
VOLUME
VOLUME
VOLUME
VOLUME
VOLUME
VOLUME
CLOCK
DIGITAL
FILTER
DIGITAL
FILTER
DIGITAL
FILTER
⌺-⌬
DAC
⌺-⌬
DAC
⌺-⌬
DAC
AD1839
VREF
OUTL1
OUTR1
OUTL2
OUTR2
OUTL3
OUTR3
FILTD
FILTR
REV. B
DGND DGND AGND AGND AGND AGND
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
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Parameter
TDM256 MODE (Master)
tTBD BCLK Delay
tFSD FSTDM Delay
tTABD
tTDDS
tTDDH
ASDATA Delay
DSDATA1 Setup
DSDATA1 Hold
TDM256 MODE (Slave)
fAB
tTBCH
BCLK Frequency
BCLK High
tTBCL
tTFS
www.DataSheet4UttTT.FBcHoDmD
tTDDS
tTDDH
BCLK Low
FSTDM Setup
FSTDM Hold
ASDATA Delay
DSDATA1 Setup
DSDATA1 Hold
AUXILIARY INTERFACE
tAXDS
tAXDH
tDXD
fABP
Slave Mode
AAUXDATA Setup
AAUXDATA Hold
DAUXDATA Delay
AUXBCLK Frequency
tAXBH
tAXBL
tAXLS
tAXLH
Master Mode
AUXBCLK High
AUXBCLK Low
AUXLRCLK Setup
AUXLRCLK Hold
tAUXLRCLK
tAUXBCLK
AUXLRCLK Delay
AUXBCLK Delay
Specifications subject to change without notice.
Min
15
15
256 ϫ fS
15
15
10
10
15
15
10
10
15
64 ϫ fS
15
15
10
10
5
15
Max
20
5
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MCLK
PD/RST
tMCLK
tMH
tML
tPDR
Figure 1. MCLK and PD/RST Timing
AD1839
Comments
From MCLK Rising
From BCLK Rising
From BCLK Rising
To BCLK Falling
From BCLK Falling
To BCLK Falling
From BCLK Falling
From BCLK Rising
To BCLK Falling
From BCLK Falling
To AUXBCLK Rising
From AUXBCLK Rising
From AUXBCLK Falling
To AUXBCLK Rising
From AUXBCLK Rising
From AUXBCLK Falling
From MCLK Rising
REV. B
–5–
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| Information | Total 24 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ AD1839.PDF Datasheet ] | |
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