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기능 High Performance 8-bit RISC Microcontroller
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DFPIC165X 데이터시트, 핀배열, 회로
www.DataSheet4U.com
DFPIC165X
High Performance
8-bit RISC Microcontroller
ver 2.01
OVERVIEW
The DFPIC165X is a low-cost, high per-
formance, 8-bit, fully static soft IP Core, dedi-
cated for operation with fast memory (typi-
cally on-chip). The core has been designed
with a special concern about low power con-
sumption.
The DFPIC165X is software compatible
with the industry standard PIC16C54,
PIC16C55, PIC16C56, PIC16C57 and
PIC16C58. It employs a modified RISC
architecture (2 times faster than original
implementation).
The DFPIC165X have enhanced core
features and configurable hardware stack.
The separate instruction and data buses allow
a 12 bit wide instruction word with the
separate 8 -bit wide data. The DFPIC165X
typically achieve a 2:1 code compression and
a 8:1 speed improvement over other 8-bit
microcontrollers in its class. The Core has 24
I/O lines and an 8-bit timer/counter with an 8-
bit programmable prescaller.
The power-down mode SLEEP allow user
to reduce power consumption. User can wake
up the controller from SLEEP through an user
reset or watchdog overflow. An integrated
Watchdog Timer with it's own clock signal
provides protection against software lock-up.
The DFPIC165X Microcontroller fits
perfectly in applications ranging from high-
speed automotive and appliance motor control
to low-power remote transmitters/receivers,
pointing devices and telecom processors.
Built-in power save mode and small used area
in programmable devices make this IP perfect
for applications applications with space and
power consumption limitations.
DFPIC165X is delivered with fully auto-
mated testbench and complete set of tests
allowing easy package validation at each
stage of SoC design flow.
CPU FEATURES
Software compatible with industry standard
PIC16C5X
Harvard architecture 2 times faster com-
pared to original implementation
33 instructions
12 bit wide instruction word
Up to 256 bytes of internal Data Memory
Up to 4K bytes of Program Memory
Configurable hardware stack
Power saving SLEEP mode
Fully synthesizable, static synchronous
design with no internal tri-states
Scan test ready
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.




DFPIC165X pdf, 반도체, 판매, 대치품
Indirect addressing is possible by using the
INDF register. Any instruction using INDF reg-
ister actually accesses data pointed to by the
file select register FSR. Reading INDF register
indirectly will produce 00h. Writing to the INDF
register indirectly results in a no-operation. An
effective 8-bit address is obtained from an 8-
bit FSR register.
Timer 0 – Main system’s timer and prescaler.
The DFPIC165X Timer operates in two
modes: 8-bit timer or 8-bit counter. In the
“timer mode”, timer registers are incremented
every 4 CLK periods. When the prescaler is
www.DataSheaets4sUi.gconmed into the TIMER prescale ration can
be divided by 2, 4 .. 256. In the “counter
mode” the timer register is incremented every
falling or rising edge of T0CKI pin, dependent
on T0SE bit in OPTION register.
Watchdog Timer – it is a free running timer.
WDT has own clock input separate from sys-
tem clock. It means that the WDT will run
even if the system clock is stopped by execu-
tion of SLEEP instruction. During normal op-
eration, a WDT timeout generates a Watch-
dog reset. If the device is in SLEEP mode the
WDT timeout causes the device to wake-up
and continue with normal operation.
I/O Ports – Block contains DFPIC165X’s gen-
eral purpose I/O ports and data direction reg-
isters (TRIS). The DFPIC165X has three 8-bit
full bi-directional ports PORT A, PORT B and
PORT C. Read and write accesses to the I/O
port are performed via their corresponding
SFR’s PORTA, PORTB, PORTC. The reading
instruction always reads the status of Port
pins. Writing instructions always write into the
Port latches. Each port’s pin has an corre-
sponding bit in TRISA, TRISB and TRISC reg-
isters. When the bit of TRIS register is set this
means that the corresponding bit of port is
configured as an input (output drivers are set
into the High Impedance).
OPTIONAL
PERIPHERALS
There are also available an optional pe-
ripherals, not included in presented
DFPIC165X Microcontroller Core. The op-
tional peripherals, can be implemented in mi-
crocontroller core upon customer request.
Full duplex UART
SPI – Master and Slave Serial Peripheral
Interface
Supports speeds up ¼ of system clock
Mode fault error
Write collision error
Software selectable polarity and phase of se-
rial clock SCK
System errors detection
Allows operation from a wide range of system
clock frequencies (build-in 5-bit timer)
Interrupt generation
PWM – Pulse Width Modulation Timer
2 independent 8-bit PWM channels, concate-
nated on one 16-bit PWM channel
Software-selectable duty from 0% to 100% and
pulse period
Software-selectable polarity of output wave-
form
I2C bus controller - Master
7-bit and 10-bit addressing modes
NORMAL, FAST, HIGH speeds
Multi-master systems supported
Clock arbitration and synchronization
User defined timings on I2C lines
Wide range of system clock frequencies
Interrupt generation
I2C bus controller - Slave
NORMAL speed 100 kbs
FAST speed 400 kbs
HIGH speed 3400 kbs
Wide range of system clock frequencies
User defined data setup time on I2C lines
Interrupt generation
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

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