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PDF AT209S Data sheet ( Hoja de datos )
| Número de pieza | AT209S | |
| Descripción | PCI Arbiter and Clock Buffer | |
| Fabricantes | AME | |
| Logotipo |  |
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AME, Inc.
AT209S
n General Description
The AT209S is an integrated device that contains a PCI
Arbiter and a Clock Buffer. PCI Arbiter extends system
PCI devices without piecing other circuit to simplify de-
sign complexity and increase systems stability.
www.DataSheet4UP.cComI Arbiter also provides STOP# input pin with that
extended PCI devices instruct the master to prematurely
end the transaction on the current data phase same as
one in PCI specification.
Clock Buffer is a high performance and low jitter zero
delay buffer that provides synchronization between the
input and output. The synchronization is established via
CLKO feed back to the input of a build-in PLL.
PCICLKI is the clock input of the Clock Buffer. In the
absence of PCICLKI input, will be in the power down mode.
In this mode, the PLL is turned off and the output buffers
are pulled low. Power down mode provides the lowest
power consumption for a standby condition.
n Features
l PCI Arbiter
Extend PCI Devices from One to Three
l PCI Clock Frequency
Support PCI Clock range from 25MHz to
66MHz
l Zero delay buffer
Generate four zero delay clock sources
Support frequency range from 25MHz to
66MHz
l All AME's Lead Free Products Meet RoHS
Standards
PCI Arbiter and Clock Buffer
Rev.A.01
1
1 page  
AME, Inc.
AT209S
n Quick Reference Data
GND = 0V; VCC = 3.3V; 0oC < Temp < 85oC
PCI Arbiter and Clock Buffer
Symbol
VCC
VSS
www.DataSheet4U.coAmVCC
AVSS
Parameter
Power pin
Ground pin
Power pin for PLL
Ground pin for PLL
Test Conditions
Min Typical Max Unit
3.15 3.3 3.45 V
0V
3.15 3.3 3.45 V
0V
Table 4. Power/Ground Pin
Symbol
Vil
Vih
Vol
Voh
Duty1
Tr
Tf
Tpd
PCICLKI
Parameter
Test Conditions
Input low voltage
Input high voltage
Output low voltage
Output high voltage
IoI=30mA; VCC3V=3.3V
Ioh=30mA; VCC3V=3.3V
Output duty cycle
(0.5*VCC as a reference)
Input duty cycle=50%
Output rise time
Output fall time
Propagation delay time
Buffer input frequency
Measure between 0.8v and 2V,
CL=30P
Measure between 0.8v and 2V,
CL=30P
Measure at 0.5*Vin & Vout,
CL=30P
Min
2
2.4
45
25M
Typical
250
Max
0.8
0.4
55
2
2
50M
Unit
V
V
V
V
%
nS
nS
nS
Hz
Table 5. Clock Buffer Block
Rev.A.01
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet AT209S.PDF ] | |
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