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PDF CY8C24894 Data sheet ( Hoja de datos )
| Número de pieza | CY8C24894 | |
| Descripción | (CY8C24x94) Mixed-Signal Array | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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PSoC® Mixed-Signal Array
CY8C24094, CY8C24794,
CY8C24894, and CY8C24994
Final Data Sheet
Features
■ CY8C24894 includes an XRES pin to support In-System Serial Programming (ISSP) and external reset control
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ Two 8x8 Multiply, 32-Bit Accumulate
❐ Low Power at High Speed
www.DataSheet❐4U3.c.0omto 5.25V Operating Voltage
❐ Industrial Temperature Range: -40°C to +85°C
❐ USB Temperature Range: -10°C to +85°C
■ Advanced Peripherals (PSoC Blocks)
❐ 6 Rail-to-Rail Analog PSoC Blocks Provide:
- Up to 14-Bit ADCs
- Up to 9-Bit DACs
- Programmable Gain Amplifiers
- Programmable Filters and Comparators
❐ 4 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
- Full-Duplex UART
- Multiple SPI™ Masters or Slaves
- Connectable to all GPIO Pins
❐ Complex Peripherals by Combining Blocks
❐ Capacitive Sensing Application Capability
■ Full-Speed USB (12 Mbps)
❐ Four Uni-Directional Endpoints
❐ One Bi-Directional Control Endpoint
❐ USB 2.0 Compliant
❐ Dedicated 256 Byte Buffer
❐ No External Crystal Required
■ Flexible On-Chip Memory
❐ 16K Flash Program Storage 50,000 Erase/
Write Cycles
❐ 1K SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■ Programmable Pin Configurations
❐ 25 mA Sink on all GPIO
❐ Pull up, Pull down, High Z, Strong, or Open
Drain Drive Modes on all GPIO
❐ Up to 48 Analog Inputs on GPIO
❐ Two 33 mA Analog Outputs on GPIO
❐ Configurable Interrupt on all GPIO
■ Precision, Programmable Clocking
❐ Internal ±4% 24/48 MHz Oscillator
❐ Internal Oscillator for Watchdog and Sleep
❐ .25% Accuracy for USB with no External
Components
■ Additional System Resources
❐ I2C™ Slave, Master, and Multi-Master to
400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
■ Complete Development Tools
❐ Free Development Software
(PSoC Designer™)
❐ Full-Featured, In-Circuit Emulator and
Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Bytes Trace Memory
Port 7
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
Analog
Drivers
Global Digital Interconnect
Global Analog Interconnect
PSoC CORE
SRAM
1K
Interrupt
Controller
SROM Flash 16K
CPUCore(M8C)
Sleep and
Watchdog
ClockSources
(Includes IMOand ILO)
DIGITAL SYSTEM
Digital
Block
Array
ANALOG SYSTEM
Analog
Block
Array
Analog
Ref.
Digital 2 Decimator
Clocks MACs Type 2
I2C
POR and LVD
System Resets
Internal
Voltage
Ref.
USB
Analog
Input
Muxing
SYSTEM RESOURCES
PSoC® Functional Overview
The PSoC® family consists of many Mixed-Signal Array with
On-Chip Controller devices. All PSoC family devices are
designed to replace traditional MCUs, system ICs, and the
numerous discrete components that surround them. The PSoC
CY8C24x94 devices are unique members of the PSoC family
because it includes a full-featured, full-speed (12 Mbps) USB
port. Configurable analog, digital, and interconnect circuitry
enable a high level of integration in a host of industrial, con-
sumer, and communication applications.
This architecture allows the user to create customized periph-
eral configurations that match the requirements of each individ-
ual application. Additionally, a fast CPU, Flash program
memory, SRAM data memory, and configurable IO are included
in a range of convenient pinouts and packages.
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources including a full-speed USB port. Config-
urable global busing allows all the device resources to be com-
bined into a complete custom system. The PSoC CY8C24x94
devices can have up to seven IO ports that connect to the glo-
bal digital and analog interconnects, providing access to 4 digi-
tal blocks and 6 analog blocks.
February 15, 2007
© Cypress Semiconductor 2004-2007 — Document No. 38-12018 Rev. *J
1
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1 page  
CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet
Development Tools
PSoC Designer is a Microsoft® Windows-based, integrated
development environment for the Programmable System-on-
Chip (PSoC) devices. The PSoC Designer IDE and application
runs on Windows NT 4.0, Windows 2000, Windows Millennium
(Me), or Windows XP. (Reference the PSoC Designer Func-
tional Flow diagram below.)
PSoC Designer helps the customer to select an operating con-
figuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
www.DataSheet4U.com
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
PSoC Designer Subsystems
PSoC
Designer
Graphical Designer
Interface
Context
Sensitive
Help
Importable
Design
Database
Device
Database
Application
Database
Project
Database
User
Modules
Library
PSoC
Designer
Core
Engine
PSoC
Configuration
Sheet
Manufacturing
Information
File
Emulation
Pod
In-Circuit
Emulator
Device
Programmer
PSoC® Overview
February 15, 2007
Document No. 38-12018 Rev. *J
5
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5 Page 
CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet
1. Pin Information
1.3 68-Pin Part Pinout
The 68-pin QFN part table and drawing below is for the CY8C24994 PSoC device.
Table 1-3. 68-Pin Part Pinout (QFN**)
Pin
No.
Type
Digital Analog
Name
1 IO
M P4[7]
2 IO
M P4[5]
3 IO
M P4[3]
4 IO
M P4[1]
5 NC
6 NC
7
Power
Vss
8 IO
M P3[7]
www.DataShee9t4U.cIOom M P3[5]
10 IO
M P3[3]
11 IO
M P3[1]
12 IO
M P5[7]
13 IO
M P5[5]
14 IO
M P5[3]
15 IO
M P5[1]
16 IO
M P1[7]
17 IO
M P1[5]
18 IO
M P1[3]
19 IO
M P1[1]
20
Power
Vss
21
USB
D+
22
USB
D-
23
Power
Vdd
24 IO
P7[7]
25 IO
P7[6]
26 IO
P7[5]
27 IO
P7[4]
28 IO
P7[3]
29 IO
P7[2]
30 IO
P7[1]
31 IO
P7[0]
32 IO
M P1[0]
33 IO
M P1[2]
34 IO
M P1[4]
35 IO
36 IO
37 IO
38 IO
39 IO
40 IO
41 IO
42 IO
43 IO
M P1[6]
M P5[0]
M P5[2]
M P5[4]
M P5[6]
M P3[0]
M P3[2]
M P3[4]
M P3[6]
44 NC
45 NC
46
Input
XRES
47 IO
48 IO
49 IO
M P4[0]
M P4[2]
M P4[4]
Description
No connection.
No connection.
Ground connection.
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
I2C Serial Clock (SCL) ISSP SCLK*.
Ground connection.
Supply voltage.
I2C Serial Data (SDA), ISSP SDATA*.
Optional External Clock Input (EXT-
CLK).
No connection.
No connection.
Active high pin reset with internal pull
down.
CY8C24994 68-Pin PSoC Device
M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
NC
NC
Vs s
M, P3[7]
M, P3[5]
M, P3[3]
M, P3[1]
M, P5[7]
M, P5[5]
M, P5[3]
M, P5[1]
I2C SCL, M, P1[7]
I2C SDA, M, P1[5]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
QFN
(Top View)
51 P2[0], M, AI
50 P4[6], M
49 P4[4], M
48 P4[2], M
47 P4[0], M
46 XRES
45 NC
44 NC
43 P3[6], M
42 P3[4], M
41 P3[2], M
40 P3[0], M
39 P5[6], M
38 P5[4], M
37 P5[2], M
36 P5[0], M
35 P1[6], M
Pin
No.
Type
Digital Analog
Name
Description
50 IO
M P4[6]
51 IO
I,M P2[0] Direct switched capacitor block input.
52 IO
I,M P2[2] Direct switched capacitor block input.
53 IO
M P2[4] External Analog Ground (AGND) input.
54 IO
M P2[6] External Voltage Reference (VREF) input.
55 IO
I,M P0[0] Analog column mux input.
56 IO
I,M P0[2] Analog column mux input and column output.
57 IO
I,M P0[4] Analog column mux input and column output.
58 IO
I,M P0[6] Analog column mux input.
59
Power
Vdd Supply voltage.
60
Power
Vss Ground connection.
61 IO
I,M P0[7] Analog column mux input, integration input #1
62 IO
IO,M P0[5] Analog column mux input and column output, integra-
tion input #2.
63 IO
IO,M P0[3] Analog column mux input and column output.
64 IO
I,M P0[1] Analog column mux input.
65 IO
M P2[7]
66 IO
67 IO
68 IO
M P2[5]
I,M P2[3] Direct switched capacitor block input.
I,M P2[1] Direct switched capacitor block input.
LEGENDA = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input.
* These are the ISSP pins, which are not High Z at POR. See the PSoC Mixed-Signal Array Technical Reference Manual for details.
** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other signal.
February 15, 2007
Document No. 38-12018 Rev. *J
11
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| Páginas | Total 48 Páginas | |
| PDF Descargar | [ Datasheet CY8C24894.PDF ] | |
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