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부품번호 WCSN0436V1P 기능
기능 128Kx36 Pipelined SRAM
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WCSN0436V1P 데이터시트, 핀배열, 회로
Y7C1350B
WCSN0436V1P
Features
128Kx36 Pipelined SRAM with NoBL™ Architecture
Functional Description
• Pin compatible and functionally equivalent to ZBT™
devices IDT71V546, MT55L128L36P, and MCM63Z736
• Supports 166-MHz bus operations with zero wait states
— Data is transferred on every clock
• Internally self-timed output buffer control to eliminate
the need to use OE
• Fully registered (inputs and outputs) for pipelined
operation
www.DataSheetB4Uy.tceomWrite capability
• 128K x 36 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
— 3.8 ns (for 150-MHz device)
— 4.0 ns (for 143-MHz device)
— 4.2 ns (for 133-MHz device)
— 5.0 ns (for 100-MHz device)
— 7.0 ns (for 80-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100 TQFP package
• Burst Capability—linear or interleaved burst order
• Low standby power (17.325 mW max.)
Logic Block Diagram
CLK
ADV/LD
A[16:0] 17
CEN
CE1
CE2
CE3
WE
BWS[3:0]
MODE
CONTROL
and WRITE
LOGIC
17
The WCSN0436V1P is a 3.3V, 128K by 36 synchronous-pipe-
lined Burst SRAM designed specifically to support unlimited
true back-to-back Read/Write operations without the insertion
of wait states. The WCSN0436V1P is equipped with the ad-
vanced No Bus Latency™ (NoBL™) logic required to enable
consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of the SRAM, especially in systems that require
frequent Write/Read transitions.The WCSN0436V1P is
pin/functionally compatible to ZBT SRAMsIDT71V546,
MT55L128L36P, and MCM63Z736.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 3.5 ns (166-MHz device).
Write operations are controlled by the four Byte Write Select
(BWS[3:0]) and a Write Enable (WE) input. All writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
CE
DaDta-In
Q
REG.
36
36
128Kx36
MEMORY
ARRAY
36
36
DQ[31:0]
DP[3:0]
OE
Selection Guide
.
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
.
.
Commercial
Commercial
-166
3.5
400
5
-150
3.8
375
5
-143
4.0
350
5
-133
4.2
300
5
-100
5.0
250
5
-80
7.0
200
5
Document#: 38-05246
Revised Jan 06,2002




WCSN0436V1P pdf, 반도체, 판매, 대치품
WCSN0436V1P
Pin Definitions (continued)
Pin Number
5, 10, 17, 21,
26, 40, 55, 60,
64, 67, 71, 76,
90
83, 84
Name
VSS
NC
I/O
Ground
-
38, 39, 42, 43 DNU
-
Description
Ground for the device. Should be connected to ground of the system.
No connects. Reserved for address inputs for depth expansion. Pin 83 and 84 will
be used for 256K and 512K depths respectively.
Do Not Use pins. These pins should be left floating or tied to VSS.
Introduction
www.DataShFeuetn4cUt.icoonmal Overview
The WCSN0436V1P is a synchronous-pipelined Burst SRAM
designed specifically to eliminate wait states during
Write/Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (tCO) is 3.5 ns (166-MHz de-
vice).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The ac-
cess can either be a read or write operation, depending on the
status of the Write Enable (WE). BWS[3:0] can be used to con-
duct byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been de-
selected in order to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs (A0A16)
is latched into the Address Register and presented to the
memory core and control logic. The control logic determines
that a read access is in progress and allows the requested
data to propagate to the input of the output register. At the
rising edge of the next clock the requested data is allowed to
propagate through the output register and onto the data bus
within 3.5 ns (166-MHz device) provided OE is active LOW.
After the first clock of the read access the output buffers are
controlled by OE and the internal control logic. OE must be
driven LOW in order for the device to drive out the requested
data. During the second clock, a subsequent operation
(Read/Write/Deselect) can be initiated. Deselecting the device
is also pipelined. Therefore, when the SRAM is deselected at
clock rise by one of the chip enable signals, its output will
three-state following the next clock rise.
Burst Read Accesses
The WCSN036V1p has an on-chip burst counter that allows
the user the ability to supply a single address and conduct up
to four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap-around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
the state of chip enables inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to A0A16 is loaded
into the Address Register. The write signals are latched into
the Control Logic block.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ[31:0] and
DP[3:0]. In addition, the address for the subsequent access
(Read/Write/Deselect) is latched into the Address Register
(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ[31:0] and
DP[3:0] (or a subset for byte write operations, see Write Cycle
Description table for details) inputs is latched into the device
and the write is complete.
The data written during the Write operation is controlled by
BWS[3:0] signals. The WCSN0436V1P provides byte write ca-
pability that is described in the Write Cycle Description table.
Asserting the Write Enable input (WE) with the selected Byte
Write Select (BWS[3:0]) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write mecha-
nism has been provided to simplify the write operations. Byte
write capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to sim-
ple byte write operations.
Because the WCSN0436V1P is a common I/O device, data
should not be driven into the device while the outputs are ac-
tive. The Output Enable (OE) can be deasserted HIGH before
presenting data to the DQ[31:0] and DP[3:0] inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ[31:0]
Document #: 38-05246 Rev. **
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WCSN0436V1P 전자부품, 판매, 대치품
WCSN0436V1P
Electrical Characteristics Over the Operating Range
Parame-
ter
VDD
VDDQ
VOH
VOL
VIH
VIL
www.DataSheIeXt4U.com
IOZ
ICC
ISB1
ISB2
ISB3
Description
Test Conditions
Min.
Power Supply Voltage
3.135
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[9]
VDD = Min., IOH = –4.0 mA[11]
VDD = Min., IOL = 8.0 mA[11]
3.135
2.4
2.0
0.3
Input Load Current
Input Current of
MODE
GND VI VDDQ
5
30
Output Leakage
Current
GND VI VDDQ, Output Disabled
5
VDD Operating
Supply
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
5.0-ns cycle, 166 MHz
6.6-ns cycle, 150 MHz
7.0-ns cycle, 143 MHz
7.5-ns cycle, 133 MHz
10.0-ns cycle, 100 MHz
12.5-ns cycle, 80 MHz
Automatic CE
Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN VIH or VIN VIL
f = fMAX = 1/tCYC
5.0-ns cycle, 166 MHz
6.6-ns cycle, 150 MHz
7.0-ns cycle, 143 MHz
7.5-ns cycle, 133 MHz
10.0-ns cycle, 100 MHz
12.5-ns cycle, 80 MHz
Automatic CE
Power-Down
Current—CMOS
Inputs
Max. VDD, Device Deselected,
VIN 0.3V or VIN >
VDDQ – 0.3V, f = 0
All speed grades
Automatic CE
Power-Down
Current—CMOS
Inputs
Max. VDD, Device Deselected, or
VIN 0.3V or VIN > VDDQ – 0.3V
f = fMAX = 1/tCYC
5.0-ns cycle, 166 MHz
6.6-ns cycle, 150 MHz
7.0-ns cycle, 143 MHz
7.5-ns cycle, 133 MHz
10.0-ns cycle, 100 MHz
12.5-ns cycle, 80 MHz
Max.
3.465
3.465
0.4
VDD + 0.3V
0.8
5
30
5
400
375
350
300
250
200
80
70
60
50
40
35
5
70
60
50
40
30
25
Unit
V
V
V
V
V
V
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Note:
11. The load used for VOH and VOL testing is shown in Figure (b) of the AC Test Loads.
Document #: 38-05246 Rev. **
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WCSN0436V1P

128Kx36 Pipelined SRAM

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