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PDF STP15NM60ND Data sheet ( Hoja de datos )

Número de pieza STP15NM60ND
Descripción N-channel Power MOSFET
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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No Preview Available ! STP15NM60ND Hoja de datos, Descripción, Manual

STB15NM60ND - STF/I15NM60ND
STP15NM60ND - STW15NM60ND
N-channel 600 V - 0.27 - 14 A - FDmesh™ II Power MOSFET
D2PAK, I2PAK, TO-220, TO-220FP, TO-247
Features
Type
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VDSS (@Tjmax) RDS(on) max ID
STB15NM60ND
14 A
STF15NM60ND
STI15NM60ND
650 V
14 A
0.299 14 A(1)
STP15NM60ND
14 A
STW15NM60ND
14 A
1. Limited only by maximum temperature allowed
The worldwide best RDS(on)* area amongst the
fast recovery diode devices
100% avalanche tested
Low input capacitance and gate charge
Low gate input resistance
Extremely high dv/dt and avalanche
capabilities
Application
Switching applications
Description
The FDmesh™ II series belongs to the second
generation of MDmesh™ technology. This
revolutionary Power MOSFET associates a new
vertical structure to the company's strip layout
and associates all advantages of reduced on-
resistance and fast switching with an intrinsic fast-
recovery body diode.Strongly recommended for
bridge topologies, in ZVS phase-shift converters.
3
1
D2PAK
3
2
1
TO-220
3
2
1
TO-247
123
I²PAK
3
2
1
TO-220FP
Figure 1. Internal schematic diagram
Table 1. Device summary
Order codes
Marking
STB15NM60ND
STF15NM60ND
STI15NM60ND
STP15NM60ND
STW15NM60ND
15NM60ND
15NM60ND
15NM60ND
15NM60ND
15NM60ND
April 2008
Rev 2
Package
D2PAK
TO-220FP
I2PAK
TO-220
TO-247
Packaging
Tape and reel
Tube
Tube
Tube
Tube
1/19
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19

1 page




STP15NM60ND pdf
STP15NM60ND - STF/I15NM60ND - STB15NM60ND - STW15NM60ND Electrical characteristics
2 Electrical characteristics
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(TCASE=25°C unless otherwise specified)
Table 5. On/off states
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
V(BR)DSS
Drain-source breakdown
voltage
dv/dt(1) Drain-source voltage slope
IDSS
Zero gate voltage drain
current (VGS = 0)
IGSS
VGS(th)
RDS(on)
Gate body leakage current
(VDS = 0)
Gate threshold voltage
Static drain-source on
resistance
ID = 1 mA, VGS= 0
VDD = 480 V,ID = 14 A,
VGS = 10 V
VDS = Max rating,
VDS = Max rating,@125 °C
VGS = ±20 V
VDS= VGS, ID = 250 µA
VGS= 10 V, ID= 7 A
600
3
V
30 V/ns
1 µA
100 µA
100 nA
4 5V
0.27 0.299
1. Value measured at turn off under inductive load
Table 6. Dynamic
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
gfs(1)
Ciss
Coss
Crss
Forward transconductance
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS =15 V, ID= 7 A
VDS = 50 V, f =1 MHz,
VGS = 0
10
1250
65
5
S
pF
pF
pF
Coss
(2)
eq.
Equivalent output
capacitance
VGS = 0, VDS = 0V to 480 V
180
pF
Rg Gate input resistance
f=1 MHz Gate DC Bias=0
Test signal level=20 mV
open drain
4
Qg Total gate charge
Qgs Gate-source charge
Qgd Gate-drain charge
VDD = 480 V, ID = 14 A
VGS = 10 V
(see Figure 19)
40 nC
8 nC
22 nC
1. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS
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STP15NM60ND arduino
STP15NM60ND - STF/I15NM60ND - STB15NM60ND - STW15NM60ND Package mechanical data
4 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
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