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1GW3B2AN6 데이터시트 PDF




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부품번호 1GW3B2AN6 기능
기능 NAND Flash Memory
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로고 ST Microelectronics 로고


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1GW3B2AN6 데이터시트, 핀배열, 회로
NAND512-B, NAND01G-B NAND02G-B
NAND04G-B NAND08G-B
512 Mbit, 1 Gbit, 2 Gbit, 4 Gbit, 8 Gbit
2112 Byte/1056 Word Page, 1.8V/3V, NAND Flash Memory
PRELIMINARY DATA
FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
www.DataSheet4U.com
– Up to 8 Gbit memory array
– Up to 64Mbit spare area
– Cost effective solutions for mass storage
applications
NAND INTERFACE
– x8 or x16 bus width
– Multiplexed Address/ Data
– Pinout compatibility for all densities
SUPPLY VOLTAGE
– 1.8V device: VDD = 1.7 to 1.95V
– 3.0V device: VDD = 2.7 to 3.6V
PAGE SIZE
– x8 device: (2048 + 64 spare) Bytes
– x16 device: (1024 + 32 spare) Words
BLOCK SIZE
– x8 device: (128K + 4K spare) Bytes
– x16 device: (64K + 2K spare) Words
PAGE READ / PROGRAM
– Random access: 25µs (max)
– Sequential access: 50ns (min)
– Page program time: 300µs (typ)
COPY BACK PROGRAM MODE
– Fast page copy without external buffering
CACHE PROGRAM AND CACHE READ
MODES
– Internal Cache Register to improve the
program and read throughputs
FAST BLOCK ERASE
– Block erase time: 2ms (typ)
STATUS REGISTER
ELECTRONIC SIGNATURE
CHIP ENABLE ‘DON’T CARE’
– for simple interface with microcontroller
AUTOMATIC PAGE 0 READ AT POWER-UP
– Boot from NAND support
SERIAL NUMBER OPTION
Figure 1. Packages
TSOP48 12 x 20mm
USOP48 12 x 17 x 0.65mm
FBGA
VFBGA63 9.5 x 12 x 1mm
TFBGA63 9.5 x 12 x 1.2mm
LFBGA63 9.5 x 12 x 1.4mm
DATA PROTECTION
– Hardware and Software Block Locking
– Hardware Program/Erase locked during
Power transitions
DATA INTEGRITY
– 100,000 Program/Erase cycles
– 10 years Data Retention
RoHS COMPLIANCE
– Lead-Free Components are Compliant
with the RoHS Directive
DEVELOPMENT TOOLS
– Error Correction Code software and
hardware models
– Bad Blocks Management and Wear
Leveling algorithms
– PC Demo board with simulation software
– File System OS Native reference software
– Hardware simulation models
February 2005
1/59
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.




1GW3B2AN6 pdf, 반도체, 판매, 대치품
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Table 8. Address Definitions, x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. Address Definitions, x16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
COMMAND SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DEVICE OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Read Memory Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
www.DataSheet4U.comPage Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9. Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10.Random Data Output During Sequential Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Cache Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 11.Cache Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Sequential Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Random Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12.Page Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13.Random Data Input During Sequential Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 11. Copy Back Program x8 Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 12. Copy Back Program x16 Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14.Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 15.Page Copy Back Program with Random Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Cache Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 16.Cache Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 17.Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Write Protection Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
P/E/R Controller and Cache Ready/Busy Bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
P/E/R Controller Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Cache Program Error Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Error Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SR4, SR3 and SR2 are Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 13. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 14. Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 15. Electronic Signature Byte/Word 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Automatic Page 0 Read at Power-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Automatic Page 0 Read Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 18.Automatic Page 0 Read at Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DATA PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Blocks Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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1GW3B2AN6 전자부품, 판매, 대치품
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
SUMMARY DESCRIPTION
The NAND Flash 2112 Byte/ 1056 Word Page is a
family of non-volatile Flash memories that uses
NAND cell technology. The devices range from
512 Mbits to 8 Gbits and operate with either a 1.8V
or 3V voltage supply. The size of a Page is either
2112 Bytes (2048 + 64 spare) or 1056 Words
(1024 + 32 spare) depending on whether the de-
vice has a x8 or x16 bus width.
The address lines are multiplexed with the Data In-
put/Output signals on a multiplexed x8 or x16 In-
www.DataSheet4Up.cuotm/Output bus. This interface reduces the pin
count and makes it possible to migrate to other
densities without changing the footprint.
Each block can be programmed and erased over
100,000 cycles. To extend the lifetime of NAND
Flash devices it is strongly recommended to imple-
ment an Error Correction Code (ECC).
The devices have hardware and software security
features:
A Write Protect pin is available to give a
hardware protection against program and
erase operations.
A Block Locking scheme is available to
provide user code and/or data protection.
The devices feature an open-drain Ready/Busy
output that can be used to identify if the Program/
Erase/Read (P/E/R) Controller is currently active.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor.
A Copy Back Program command is available to
optimize the management of defective blocks.
When a Page Program operation fails, the data
can be programmed in another page without hav-
ing to resend the data to be programmed.
Each device has Cache Program and Cache Read
features which improve the program and read
throughputs for large files. During Cache Program-
ming, the device loads the data in a Cache Regis-
ter while the previous data is transferred to the
Page Buffer and programmed into the memory ar-
ray. During Cache Reading, the device loads the
data in a Cache Register while the previous data
is transferred to the I/O Buffers to be read.
All devices have the Chip Enable Don’t Care fea-
ture, which allows code to be directly downloaded
by a microcontroller, as Chip Enable transitions
during the latency time do not stop the read oper-
ation.
Two options are available for the NAND Flash
2112 Byte/ 1056 Word Page family:
Automatic Page 0 Read at Power-up, which
allows the microcontroller to directly download
the boot code from page 0.
A Unique Identifier (serial number), which
allows each device to be uniquely identified.
The Unique Identifier options is subject to an NDA
(Non Disclosure Agreement) and so not described
in the datasheet. For more details of this option
contact your nearest ST Sales office.
The devices are available in the following packag-
es:
TSOP48 (12 x 20mm) for all products
USOP48 (12 x 17 x 0.65mm) for 512Mb
and1Gb products
VFBGA63 (9.5 x 12 x 1mm, 0.8mm pitch) for
512Mb and 1Gb products
TFBGA63 (9.5 x 12 x 1.2mm, 0.8mm pitch) for
2Gb Dual Die products
LFBGA63 (9.5 x 12 x 1.4mm, 0.8mm pitch) for
8Gb Quadruple Die products.
For information on how to order these options refer
to Table 31., Ordering Information Scheme. De-
vices are shipped from the factory with Block 0 al-
ways valid and the memory content bits, in valid
blocks, erased to ’1’.
See Table 2., Product Description, for all the de-
vices available in the family.
7/59

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NAND Flash Memory

ST Microelectronics
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