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PDF MC33927 Data sheet ( Hoja de datos )
| Número de pieza | MC33927 | |
| Descripción | Three-Phase Field Effect Transistor Pre-Driver | |
| Fabricantes | Freescale Semiconductor | |
| Logotipo |  |
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Freescale Semiconductor
Advance Information
Document Number: MC33927
Rev. 2.0, 8/2007
Three-Phase Field Effect
Transistor Pre-Driver
33927
The 33927 is a Field Effect Transistor (FET) pre-driver designed for
three-phase motor control and similar applications. The integrated
circuit (IC) uses SMARTMOS™ technology.
The IC contains three high-side FET pre-drivers and three low-side
FET pre-drivers.Three external bootstrap capacitors provide gate
charge to the high side FETs.
The IC interfaces to a MCU via six direct input control signals, a SPI
port for device setup and asynchronous reset, enable and interrupt
signals. Both 5.0V and 3.0V logic level inputs are accepted and 5.0V
www.DataSheelto4gUic.colemvel outputs are provided.
Features
• Fully specified from 8.0V to 40V covers 12V and 24V automotive
systems
• Extended operating range from 6.0V to 58V covers 12V and 42V
systems
• 1.0A gate drive capability with protection
• Protection against reverse charge injection from CGD and CGS of
external FETs
• Includes a charge pump to support full FET drive at low battery
voltages
• Deadtime is programmable via the SPI port
• Simultaneous output capability enabled via safe SPI command
• Pb-Free Packaging Designated by Suffix Code EK
VBAT
33927
VPUMP
PUMP
VPWR
VLS
VBAT
PA_HS_G
PB_HS_G
PC_HS_G
MCU
OR
DSP
VDD
PA_HS_S
VSS
PB_HS_S
PC_HS_S
3
PX_HS
3
PX_LS
3 PHASEX
PA_LS_G
CS PB_LS_G
SI PC_LS_G
SCLK
SO PGND_X
RST
INT
EN1
EN2
AMP_P
AMP_N
GND AMP_OUT
FET PRE-DRIVER
EK SUFFIX (Pb-FREE)
98ASA99334D
54-PIN SOICW-EP
ORDERING INFORMATION
Device
MCZ33927EK/R2
Temperature
Range (TA)
-40°C to 125°C
Package
54 SOICW-EP
RSEN
Figure 1. 33927 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
1 page  
PIN CONNECTIONS
Table 1. 33927 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 20.
Pin Pin Name Pin Function Formal Name
Definition
46 PA_HS_S Power Input Phase A High-Side Source connection for Phase A High-Side FET
Source
47 PA_HS_G Power Output Phase A High-Side Gate Drive for output Phase A High-Side
Gate Drive
48 PA_BOOT Analog Input Phase A Bootstrap Bootstrap capacitor for Phase A
51 VLS Analog Output VLS Regulator VLS regulator output. Power supply for the gate drives
54
VPWR Power Input
Voltage Power
Power supply input for gate drives
www.DataSheet4U.com
EP
Ground
Exposed Pad
Device will perform as specified with the Exposed Pad un-terminated
(floating) however, it is recommended that the Exposed Pad be terminated
to pin 29 (VSS) and system ground
Analog Integrated Circuit Device Data
Freescale Semiconductor
33927
5
5 Page 
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 8.0V ≤ VPWR = VBAT ≤ 40V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol Min Typ Max Unit
CURRENT SENSE AMPLIFIER (CONTINUED)
Input Offset Current
IOS = IAMP_P - IAMP_N
Input Offset Current Drift (24)
Output Voltage
High-Level with RLOAD = 10 kΩ to VSS
Low-Level with RLOAD = 10 kΩ to VDD
www.DataSheet4DUif.fceoremntial Input Resistance
Output Short Circuit Current
Common-Mode Input Capacitance at 10 kHz (24)(25)
Common-Mode Rejection Ratio at DC
CMRR = 20*Log ((VOUT_diff/VIN_diff) * (VIN_CM/VOUT_CM))
Large Signal Open Loop Voltage Gain (DC) (24)(25)
Gain Margin at Gain = 5.0 (24)(25)
Nonlinearity (24)(25)
RL = 1kΩ, CL = 500pF, 0.3 < VO < 4.8V, Gain = 5.0 to 15
IOS
δIOS/δT
VOH
VOL
RI
ISC
CI
CMRR
AOL
AM
NL
-80
–
VDD-0.2
–
1.0
5.0
–
60
–
–
-1.0
–
40
–
–
–
–
–
80
60
5.0
–
+80
–
VDD
0.2
–
–
10
–
–
–
+1.0
nA
pA/°C
V
MΩ
mA
pF
dB
dB
dB
%
Notes
24. This parameter is a design characteristic, not production tested.
25. Without considering any offsets such as input offset voltage, internal mismatch and assuming no tolerance error in external resistors.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33927
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MC33927.PDF ] | |
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