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PDF MS8104160 Data sheet ( Hoja de datos )
| Número de pieza | MS8104160 | |
| Descripción | Dual FIFO | |
| Fabricantes | OKI electronic componets | |
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FEDS8104160-03
OKI Semiconductor
MS8104160
REVISION3 2000.9.28
(262,214-word x 8-Bits) x 2 Dual FIFO
GENERAL DESCRIPTION
www.DataSheet4U.com The MS8104160 is a single-chip 4Mb FIFO functionally composed of two OKI 2Mb FIFO
(First-In First-Out) memories which were designed for 256k x 8-bit high-speed
asynchronous read/write operation.
The read clocks and the write clocks of each of the 2Mb FIFO memories are connected in
common. The MS8104160, functionally compatible with Oki's 2Mb FIFO memory
(MSM518222A), can be used as a x16 configuration FIFO.
The MS8104160 is a field memory for wide or low end use in general commodity TVs and
VTRs exclusively and is not designed for high end use in professional graphics systems,
which require long term picture storage, data storage, medical use and other storage
systems.
The MS8104160 provides independent control clocks to support asynchronous read and
write operations. Different clock rates are also supported, which allow alternate data rates
between write and read data streams.
The MS8104160 provides high speed FIFO (First-in First-out) operation without external
refreshing: MS8104160 refreshes its DRAM storage cells automatically, so that it appears
fully static to the users.
Moreover, fully static type memory cells and decoders for serial access enable the refresh
free serial access operation, so that serial read and/or write control clock can be halted
high or low for any duration as long as the power is on. Internal conflicts of memory access
and refreshing operations are prevented by special arbitration logic.
The MS8104160’s function is simple, and similar to a digital delay device whose delay-bit-
length is easily set by reset timing. The delay length and the number of read delay clocks
between write and read, is determined by externally controlled write and read reset timings.
Additional SRAM serial registers, or line buffers for the initial access of 256 x 16-bit enable
high speed first-bit-access with no clock delay just after the write or read reset timings.
Additionally, the MS8104160 has a write mask function or input enable function (IE), and
read- data skipping function or output enable function (OE). The differences between write
enable (WE) and input enable (IE), and between read enable (RE) and output enable (OE)
are that WE and RE can stop serial write/read address increments, but IE and OE cannot
stop the increment, when write/read clocking is continuously applied to MS8104160. The
input enable (IE) function allows the user to write into selected locations of the memory
only, leaving the rest of the memory contents unchanged. This facilitates data processing to
display a “picture in picture” on a TV screen.
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MS8104160
FEDS8104160-03
OKI Semiconductor
PIN DESCRIPTION
Data Inputs: (DIN 10 - 17)
These pins are used for serial data inputs.
Write Reset: RSTW1
The first positive transition of SWCK after RSTW becomes high resets the write address
www.DataSheet4U.com pointers to zero. RSTW1 setup and hold times are referenced to the rising edge of SWCK.
Because the write reset function is solely controlled by the SWCK rising edge after the high
level of RSTW, the states of WE1 and IE1 are ignored in the write reset cycle. Before
RSTW1 may be brought high again for a further reset operation, it must be low for at least
two SWCK cycles.
Write Enable: WE1
WE1 is used for data write enable/disable control. WE1 high level enables the input, and
WE1 lowlevel disables the input and holds the internal write address pointer. There are no
WE1 disabletime (low) and WE1 enable time (high) restrictions, because the MS8104160
is in fully static operation as long as the power is on. Note that WE1 setup and hold times
are referenced to the rising edge of SWCK.
Input Enable: IE1
IE1 is used to enable/disable writing into memory. IE1 high level enables writing. The
internal write address pointer is always incremented by cycling SWCK regardless of the
IE1 level. Note that IE1 setup and hold times are referenced to the rising edge of SWCK.
Data Out: (DOUT 10 - 17)
These pins are used for serial data outputs.
Read Reset: RSTR1
The first positive transition of SRCK after RSTR1 becomes high resets the read address
pointers to zero. RSTR1 setup and hold times are referenced to the rising edge of SRCK.
Because the read reset function is solely controlled by the SRCK rising edge after the high
level of RSTR, the states of RE1 and OE1 are ignored in the read reset cycle. Before
RSTR may be brought high again for a further reset operation, it must be low for at least
*two SRCK cycles.
Read Enable: RE1
The function of RE1 is to gate of the SRCK clock for incrementing the read pointer. When
RE1 is high before the rising edge of SRCK, the read pointer is incremented. When RE1 is
low, the read pointer is not incremented. RE1 setup times (tRENS and tRDSS) and RE1
hold times (tRENH and tRDSH) are referenced to the rising edge of the SRCK clock.
Output Enable: OE1
OE1 is used to enable/disable the outputs. OE1 high level enables the outputs. The
internal read address pointer is always incremented by cycling SRCK regardless of the
OE1 level. Note that OE1 setup and hold times are referenced to the rising edge of SRCK.
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MS8104160
FEDS8104160-03
OKI Semiconductor
OPERATION MODE
Write Operation Cycle (MODE2=Vss)
The write operation is controlled by seven control signals, SWCK, RSTW1, RSTW2, WE1,
WE2 and IE1, IE2. Port1 write operation is accomplished by cycling SWCK, and holding
WE1 high after the write address pointer reset operation or RSTW1. RSTW1 must be
preformed for internal circuit initialization before Write operation.
www.DataSheet4U.com Each write operation, which begins after RSTW1, must contain at least 80 active write
cycles, i.e. SWCK cycles while WE1 and IE1 are high. To transfer the last data to the DRAM
array, which at that time is stored in the serial data registers attached to the DRAM array, an
RSTW1 operation is required after the last SWCK cycle.
Note that every write timing of MS8104160 is delayed by one clock compared with read
timings for easy cascading without any interface delay devices.
Setting MODE1 to the Vss level starts write data accessing in the cycle in which RSTW1,
WE1, and IE1 control signals are input.
Setting MODE1 to the Vcc level starts write data accessing in the cycle subsequent to the
cycle in which RSTW1, WE1, and IE1 control signals are input.
These operation are the same for Port1 and Port2.
Settings of WE1, 2 and IE1, 2 to the operation mode of Write address pointer and
Data input.
WE1,2
H
H
L
IE1,2
H
L
X
Internal Write address pointer
Data input
Incremented
Input
Halted
Not input
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Write Operation Cycle (MODE2=Vcc)
The write Operation is controlled by seven control signals, SWCK, RSTW1, RSTW2, WE1,
WE2, and IE1, IE2. Port1 write operation is accomplished by cycling SWCK and holding
both WE1 and IE1 low after the write address pointer reset operation or RSTW1. RSTW1
must be performed for internal circuit initialization before write operation.
Each write operation, which begins after RSTW1, must contain at least 80 active write
cycle, i.e. SWCK cycles while WE1 and IE1 are high. To transfer the last data to the DRAM
array, which at that time is stored in the serial data registers attached to the DRAM array,
an RSTW1 operation is required after the last SWCK cycle.
Note that every write timing of MS8104160 is delayed by one clock compared with read
timings for easy cascading without any interface delay devices.
Setting MODE1 to the Vss level starts write data accessing in the cycle in which
RSTW1.WE1, and IE1 control signals are input.
Setting MODE1 to the Vcc level starts write data accessing in the cycle in which RSTW1,
WE1, and IE1 control signals are input.
Setting MODE1 to the Vcc level starts write data accessing in the cycle subsequent to the
cycle in which RSTW1, WE1, and IE1 control signals are input.
These operations are the same for port1 and Port2.
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| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet MS8104160.PDF ] | |
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