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부품번호 AD7280 기능
기능 Lithium Ion Battery Monitoring System
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로고 Analog Devices 로고


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AD7280 데이터시트, 핀배열, 회로
Preliminary Technical Data
FEATURES
12-bit ADC, 1us per channel conversion time
6 Analog Input Channels, CM range 0.5V to 27.5V
6 Temperature Measurements Inputs.
On Chip Voltage Regulator
Cell Balancing Interface
Daisy Chain Interface
www.DataShee3t4pUp.cmomReference
Low Quiescent Current
High Input Impedance
Serial Interface with Alert Function
1 SPI interface for up to 300 channels
On Chip Registers for Channel Sequencing
VDD Operating Range 7.5V to 30V
Temperature Range -40 oC to 105oC
48 lead LQFP and LFCSP Packages
APPLICATIONS
Lithium Ion Battery Monitoring
Nickel Metal Hydride Battery Monitoring
GENERAL DESCRIPTION
The AD72801 contains all the functions required for general
purpose monitoring of stacked Lithium Ion batteries as used in
Hybrid Electric Vehicles. The part has multiplexed analog input
and temperature measurement channels for up to six cells of
battery management. An internal 3-ppm reference is provided
to drive the ADC. The ADC resolution is 12 bits with a 1 Msps
throughput rate offering a 1µs conversion time.
The AD7280 operates from just one VDD supply which has a
range of 7.5V to 30V (with an absolute max rating of 33V). The
part provides 6 pseudo differential analog input channels to
accommodate large common mode signals across the full VDD
range. Each channel allows an input signal range, Vin(+) --
Vin(-), of 0V to 5V. The input pins assume a series stack of 6
cells. In addition the part can accommodate 6 external sensors
for temperature measurement.
The AD7280 includes on chip registers which allow a sequence
of channel measurements to be programmed to suit the
applications requirements.
Lithium Ion Battery
Monitoring System
AD7280
FUNCTIONAL BLOCK DIAGRAM
VDD
Vin(6)
Vin(5)
Vin(4)
Vin(3)
Vin(2)
Vin(1)
Vin(0)
AD7280
MUX
VT(6)
VT(5)
VT(4)
VT(3)
VT(2)
VT(1)
VT TERM
VREF
CREF
REFGND
DAIS Y CHAIN
INTER FACE
++
--
CLOCK
2.5V
REF
CB1
CB6
CEL L
BALANCING
INTER FACE
REGUL ATOR
12 BIT ADC
CONTRO L LOGIC
& SELF TEST
LIMIT REG
SQN LOGIC
DATA MEMO RY
SPI INTER FACE
VREG
DGND
DVCC
AVCC
VDRIVE
SCLK
S D IN
SDOUT
ALERT
CS
PD
CNVST
MASTER
Figure 1
The AD7280 also includes an Alert function which generates an
interrupt output signal if the cell voltages exceed an upper or
lower limit defined by the user. The AD7280 has balancing
interface outputs designed to control external FET transistors to
allow discharging of individual cells.
The AD7280 includes a Built In Self Test feature which
internally applies a known voltage to the ADC inputs.
There is a daisy chain interface which allows up to 50 parts to
be stacked without the need for individual device isolation.
The AD7280 requires only one supply pin which takes 7mA
under normal operation, while converting at 1 Msps.
All this functionality is provided in a 48 pin LQFP or 48 pin
LFCSP package operating over a temperature range of −40°C to
+105°C.
1 Patents Pending
Rev. PrD
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.




AD7280 pdf, 반도체, 판매, 대치품
AD7280
Preliminary Technical Data
Parameter1
Min
Typ Max Unit
Test Conditions/Comments
POWER DISSIPATION
During Conversion
300 mW
VDD = 30 V
Full Powerdown Mode
120 µW
VDD = 30 V
1 Temperature range is −40°C to +105°C.
2 For dc accuracy specifications, the LSB size for cell voltage measurements is (2VREF-1V)/4096, the LSB size for temperature measurements is 2VREF/4096.
3 ADC Unadjusted Error includes the INL of the ADC and the Gain and Offset Errors of the Vin0 to Vin6 input channels.
4 Total Unadjusted Error includes the INL of the ADC and the Gain and Offset Errors of the Vin0 to Vin6 input channels as well as the temperature coefficient of the 2.5V reference.
5 ADC Unadjusted Error includes the INL of the ADC and the Gain and Offset Errors of the VT input channels.
6 Total Unadjusted Error includes the INL of the ADC and the Gain and Offset Errors of the VT input channels as well as the temperature coefficient of the 2.5V reference.
7 This spec outlines the regulator output current which is available for external use, that is, it does not include the regulator current already being used by the AD7280.
8 CB output can be set to 0V or 5V with respect to negative terminal of cell being balanced.
9 CB1 output ramp up time is defined from the rising edge of the CS command until the CB output exceeds 4V with respect to negative terminal of cell being balanced.
www.Data1S0 ChBe1eto4uUtp.cuot mramp down time is defined from the falling edge of the CS command until the CB output falls below 50mV with respect to negative terminal of cell being
balanced. This specification is defined from the falling edge of CS as any CB outputs which on are switched off for the duration of a CS low pulse and will be switched
back on following the rising edge of that CS pulse.
11 CB2 to CB6 output ramp up time is defined from the rising edge of the CS command until the CB output exceeds 4V with respect to negative terminal of cell being
balanced.
12 CB2 to CB6 output ramp down time is defined from the falling edge of the CS command until the CB output falls below 50mV with respect to negative terminal of cell
being balanced. This specification is defined from the falling edge of CS as any CB outputs which on are switched off for the duration of a CS low pulse and will be
switched back on following the rising edge of that CS pulse.
TIMING SPECIFICATIONS
VDD = 7.5 V to 30 V, VSS = 0 V, DVCC = AVCC = VREG, VDRIVE = 2.7 V to 5.25 V, TA = -40oC to 105oC, unless otherwise noted.1
Table 2.
Parameter
tCONV
tDELAY
Limit at TMIN, TMAX
2.7 V ≤ VDRIVE < 4.75 V 4.75 V ≤ VDRIVE ≤ 5.25 V
610 610
50 50
Unit
ns max
ns max
fSCLK
tQUIET
10
1
200
10
1
200
kHz min
MHz max
ns min
t1 10
t2 10
t3 10
10
10
10
ns min
ns min
ns max
t4 5
t5 3
t62 20
t7 7
t8 0.3 × tSCLK
t9 0.3 × tSCLK
t10 10
t11 10
5
3
14
7
0.3 × tSCLK
0.3 × tSCLK
10
10
ns min
ns min
ns max
ns min
ns min
ns min
ns min
ns max
Test Conditions/Comments
ADC Conversion time
Propogation delay between adjacent parts on the Daisy
Chain
Frequency of serial read clock
Minimum quiet time required between the end of serial
read and the start of the next conversion
Minimum CONVST low pulse
CS falling edge to SCLK rising edge
Delay from CS falling edge until SDO is three-state
disabled
SDI setup time prior to SCLK falling edge
SDI hold time after SCLK falling edge
Data access time after SCLK falling edge
SCLK to data valid hold time
SCLK high pulse width
SCLK low pulse width
CS rising edge to SCLK rising edge
CS rising edge to SDO high impedance
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
All timing specifications given are with a 25 pF load capacitance.
2 The time required for the output to cross 0.4 V or 2.4 V.
Rev. PrD | Page 4 of 33

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AD7280 전자부품, 판매, 대치품
Preliminary Technical Data
AD7280
20
DGND
Digital Ground. Ground reference point for all digital circuitry on the AD7280. The DGND and AGND voltages
should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.
21 CS
Chip select Input. When acting as a master, that is the Master pin of the AD7280 is connected to VDD, the CS
input is used to frame the input and output data on the SPI. The CS input also frames the input and output data
on the Daisy Chain Interface when the MASTER input of the AD7280 is connected to VSS.
22
SCLK
Serial Clock Input. When acting as master the SCLK input is supplied from the DSP/uP. When acting as a slave on
the Daisy Chain this input should be connected to the SCLKhi output of the AD7280 immediately below it in
potential in the Daisy Chain.
23 SDI Serial Data Input. Data to be written to the on-chip registers is provided on this input and is clocked into the
AD7280 on the falling edge of SCLK. When acting as master this is the data input of the SPI interface. When
acting as a slave on the Daisy Chain this input acepts data from the SDOhi output of the AD7280 immediately
below it in potential in the Daisy Chain.
24
CNVST
Convert Start Input. The conversion is initiated on the falling edge of CONVST. When acting as master the
w w w . D a t a S h e e t 4 U . cCNoVSmT pulse is supplied from the DSP/uP. When acting as a slave on the Daisy Chain this input should be
connected to the CNVSThi output of the AD7280 immediately below it in potential in the Daisy Chain. This
input can also be tied to VCC and the conversion initiated through the serial interface.
25
SDOlo
Serial Data Output in Daisy Chain mode. This output should be connected to the SDIhi input of the AD7280
immediately below it in potential on the Daisy Chain. The data from each AD7280 in the Daisy Chain will be
passed through the SDOlo outputs and SDIhi inputs of each AD7280 in the chain and supplied to the uP/DSP
through the SDO output of the master AD7280.
26 SDO Serial Data Output. The conversion output data or the register output data is supplied to this pin as a serial data
stream. The bits are clocked out on the falling edge of the SCLK input, and 24 SCLKs are required to access the
data. The data is provided MSB first. In a Daisy Chain application the SDO output of the master AD7280 should
be connected to the uP/DSP. The SDO outputs of the remaining AD7280s in the chain should be terminated to
VSS through a 1kresistor. The data from each AD7280 in the Daisy Chain will be passed through the SDOlo
outputs and SDIhi inputs of each AD7280 in the chain and supplied to the uP/DSP through the SDO output of
the master AD7280. 24 SCLKs are required for each AD7280 in the chain to access the data.
27
ALERT
Digital Output. Flag to indicate over voltage, under voltage, over temperature or under temperature. The ALERT
output of the master AD7280 should be connected to the uP/DSP. The ALERT outputs of the remaining
AD7280s in the chain should be be terminated to VSS through a 1kresistor..
28
ALERTlo
Alert Output in Daisy Chain mode. The alert signal from each AD7280 in the Daisy Chain will be passed through
the ALERTlo outputs and ALERThi inputs of each AD7280 in the chain and supplied to the uP/DSP through the
ALERT output of the master AD7280. This input should be connected to the ALERThi input of the AD7280
immediately below it in potential on the Daisy Chain.
29
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.
This pin should be decoupled to DGND. The voltage range on this pin is 2.7 V to 5.25 V and may be different to
the voltage at AVCC and DVCC, but should never exceed either by more than 0.3 V.
30 AVCC Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the ADC core. The AVCC and DVCC voltages
should ideally be at the same potential. For best performance, it is recommended that the DVCC and AVCC pins
be shorted together, to ensure that the voltage difference between them never exceeds 0.3 V even on a
transient basis. This supply should be decoupled to AGND. Place 100 nF decoupling capacitors on the AVCC pin.
The AVCC supply pin should be externally connected to the VREG output.
31
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7280. This input should be at the
same potential as the base of the series connected battery cells. The AGND and DGND voltages ideally should
be at the same potential and must not be more than 0.3 V apart, even on a transient basis.
32
VTTERM
Thermistor termination resistor input.
33 to 38 VT6 to VT1 Voltage temperature input from potential divider with thermistor.
39 CREF A 100 nF decoupling capacitor to REFGND should be placed on this pin.
40 VREF Reference Output. The on-chip reference is availble on this pin for use external to the AD7280. The nominal
internal reference voltage is 2.5V, which appears at the pin. A 10 µF decoupling capacitor to REFGND is
recommended on this pin.
41 REFGND Reference Ground. This is the ground reference point for the internal bandgap reference circuitry on the
AD7280. The REFGND voltage should be at the same potential as the AGND voltage.
42
ALERThi
Alert Input in Daisy Chain mode. Flag to indicate over voltage, under voltage, over temperature or under
temperature in Daisy Chain mode. The alert signal from each AD7280 in the Daisy Chain will be passed through
the ALERTlo outputs and ALERThi inputs of each AD7280 in the chain and supplied to the uP/DSP through the
ALERT output of the master AD7280. This input should be connected to the ALERTlo output of the AD7280
immediately above it in potential on the Daisy Chain.
Rev. PrD | Page 7 of 33

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