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LHF16KA1 데이터시트 PDF




Sharp Electrionic Components에서 제조한 전자 부품 LHF16KA1은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 LHF16KA1 자료 제공

부품번호 LHF16KA1 기능
기능 Flash Memory 16M (2MB bb 8/1MB bb 16)
제조업체 Sharp Electrionic Components
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LHF16KA1 데이터시트, 핀배열, 회로
PRODUCT SPECIFICATIONS
®
Integrated Circuits Group
LH28F160S3NS-L10
Flash Memory
16M (2MB × 8/1MB × 16)
(Model No.: LHF16KA1)
Spec No.: EL128039
Issue Date: August 22, 2000




LHF16KA1 pdf, 반도체, 판매, 대치품
SHARP
LHFlGKAl
2
LH28F160S3NSLIO
16M-BIT (2MBx8/1 MBxl6)
Smart 3 Flash MEMORY
a Smart 3 Technology
- 2.7V or 3.3V VCC
- 2.7V, 3.3V or 5V Vpp
n Common Flash Interface (CFI)
- Universal & Upgradable Interface
n Scalable Command Set (SCS)
n High Speed Write Performance
- 32 Bytes x 2 plane Page Buffer
- 2.7 @Byte Write Transfer Rate
n High Speed Read Performance
- 1OOns(3.3Vk0.3V), 120ns(2.7V-3.6V)
n Enhanced Data Protection Features
- Absolute Protection with VpP=GND
- Flexible Block Locking
- Erase/Write Lockout during Power
Transitions
n Extended Cycling Capability
- 100,000 Block Erase Cycles
- 3.2 Million Block Erase Cycles/Chip
n Low Power Management
- Deep Power-Down Mode
- Automatic Power Savings Mode
Decreases ICC in Static Mode
n Operating Temperature
- 0°C to +7O”C
n Enhanced Automated Suspend Options
- Write Suspend to Read
- Block Erase Suspend to Write
- Block Erase Suspend to Read
I High-Density Symmetrically-Blocked
Architecture
- Thirty-two 64K-byte Erasable Blocks
I SRAM-Compatible Write Interface
I User-Configurable x8 or x16 Operation
n Automated Write and Erase
- Command User Interface
- Status Register
n Industry-Standard Packaging
- 56-Lead SSOP
n ETOXTM’ V Nonvolatile Flash
Technology
n CMOS Process
(P-type silicon substrate)
n Not designed or rated as radiation
hardened
.
SHARP’s LH28F160S3NS-L10 Flash memory with Smart 3 technology is a high-density, low-cost, nonvolatile,
,ead/write storage solution for a wide range of applications. Its symmetrically-blocked architecture, flexible voltage
Ind extended cycling provide for highly flexible component suitable for resident flash arrays, SlMMs and memory
:ards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For
iecure code storage applications, such as networking, where code is either directly executed out of flash or
downloaded to DRAM, the LH28F160S3NS-L10 offers three levels of protection: absolute protection with V,, at
SND, selective hardware block locking, or flexible software block locking. These alternatives give designers
ultimate control of their code security needs.
-he LH28F160S3NS-LlO is conformed to the flash Scalable Command Set (SCS) and the Common Flash Interface
CFI) specification which enable universal and upgradable interface, enable the highest system/device data transfer
ates and minimize device and system-level implementation costs.
-he LH28F160S3NSLlO is manufactured on SHARP’s 0.35pm ETOX TM* V process technology. It come in
idustry-standard package: the 56-Lead SSOP ideal for board constrained applications.
ETOX is a trademark of Intel Corporation.
Rev.1.9

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LHF16KA1 전자부품, 판매, 대치품
SHARP
LHFlGKAl
5
Symbol
*o-*20
DQo-DQ,
CEO%
CE,#
RP#
OE#
WE#
STS
WP#
BYTE#
“PP
“cc
GND
NC
Type
INPUT
INPUT/
OUTPUT
INPUT
INPUT
INPUT
INPUT
OPEN
DRAIN
OUTPUT
INPUT
INPUT
SUPPLY
SUPPLY
SUPPLY
Table 2. Pin Descriptions
Name and Function
ADDRESS INPUTS: Inputs for addresses durinq read and write operations. Addresses are
internally latched during a write cycle.
Ao: Byte Select Address. Not used in x16 mode(can be floated).
AI-AK Column Address. Selects 1 of 16 bit lines.
AsAls: Row Address. Selects 1 of 2048 word lines.
A16420 : Block Address.
DATA INPUT/OUTPUTS:
DQo-DQ,:lnputs data and commands during CUI write cycles; outputs data during memory
array, statusregister, query, and identifier code read cycles. Data pins float to high-
impedance when the chip is deselected or outputs are disabled. Data is internally latched
during a write cycle.
DQs-DQ,s:lnputs data during CUI write cycles in x16 mode; outputs data during memory
array read cycles in xl 6 mode; not used for status register, query and identifier code read
mode. Data pins float to hiqh-impedance when the chio is deselected, outouts are
disabled, or in x8 mode(By~e#=V,, ). Data is internally iatched during a write cycle.
CHIP ENABLE: Activates the device’s control logic, input buffers decoders, and sense
amplifiers. Either CE,# or CE,# Vlu deselects the device and reduces power consumotion
to standby levels. Bo?h CEr# and ‘CE,# must be VI, to select the devices.
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets
internal automation. RP# V,, enables normal operation: When driven VI,, RP# inhibits
write operations which provides data protection during power transitions. Exit from deep
power-down sets the device to read array mode.
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and arrav blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
STS (RY/BY#): Indicates the status of the internal WSM. When configured in level mode
(default mode), it acts as a RY/BY# pin. When low, the WSM is performing an internal
operation (block erase, full chip erase, (multi) word/byte write or block lock-bit
configuration). STS High Z indicates that the WSM is ready for new commands, block
erase is suspended, and (multi) word/byte write is inactive, (multi) word/byte write is
suspended or the device is in deer, Dower-down mode. For alternate confiaurations of the
/STATUS pin, see the Configuratidn’command.
1WRITE PROTECT: Master control for block locking. When VI,. Locked blocks can not be
Ierased and programmed, and block lock-bits can not be set and reset.
IBYTE ENABLE: BYTE# VI, places device in x8 mode. All data is then inout or outout on
IL.
IDQ,.,, and DQ,,, float. BYTE# V,, places the device in x16 mode , and turns off’the A0
input buffer.
IBLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE, BLOCK LOCK-
I31T CONFIGURATION POWER SUPPLY: For erasing array blocks, writing bytes or
(:onfiguring block lock-bits. With V,+V,,,,, memory contents cannot be altered.,Block
terase, full chip erase, (multi) word/bvte write and block lock-bit confiauration with an invalid
\Jpp (see DC Characteristics) produce spurious results and should n’;;t be attempted.
IDEVICE POWER SUPPLY: Internal detection confioures the device for 2.7” or 3.3”
operation. To switch from one voltage to another, ramp Vcc down to GND and then ramp
;/co to the new voltage. Do not float any power pins. With Vcc5VLk0, all write attempts to
he flash memory are inhibited. Device operations at invalid Vrr voltage (see DC
:zharacteristics ) produce spurious results and should not be afigmpted.
(iROUND: Do not float any ground pins.
r10 CONNECT: Lead is not internal connected: it may be driven or floated.
Rev. 1.9

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관련 데이터시트

부품번호상세설명 및 기능제조사
LHF16KA1

Flash Memory 16M (2MB bb 8/1MB bb 16)

Sharp Electrionic Components
Sharp Electrionic Components
LHF16KA3

Flash Memory 16M (2MB bb 8/1MB bb 16)

Sharp Electrionic Components
Sharp Electrionic Components

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