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LHF16KA4 데이터시트 PDF




Sharp Electrionic Components에서 제조한 전자 부품 LHF16KA4은 전자 산업 및 응용 분야에서
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부품번호 LHF16KA4 기능
기능 Flash Memory 16M (2MB bb 8/1MB bb 16)
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LHF16KA4 데이터시트, 핀배열, 회로
PRODUCT SPECIFICATIONS
®
Integrated Circuits Group
LH28F160S5NS-L70
Flash Memory
16M (2MB × 8/1MB × 16)
(Model No.: LHF16KA4)
Spec No.: EL128040
Issue Date: August 22, 2000




LHF16KA4 pdf, 반도체, 판매, 대치품
SHAFZP
- LHF16KA4
2
LH28F160S5NSL70
1GM-BIT (2MBx8/1 MBxl6)
Smart 5 Flash MEMORY
I Smart 5 Technology
- 5V vcc
- sv vpp
n Common Flash Interface (CFI)
- Universal & Upgradable Interface
n Scalable Command Set (SCS)
n High Speed Write Performance
- 32’Bytes x 2 plane Page Buffer
- 2pslByte Write Transfer Rate
I High Speed Read Performance
- 70ns(SV*O.25!/), 80ns(5V*OSV)
I Operating Temperature
- 0°C to +7O”C
I Enhanced Automated Suspend Options
- Write Suspend to Read
- Block Erase Suspend to Write
- Block Erase Suspend to Read
I High-Density Symmetrically-Blocked
Architecture
- Thirty-two 64K-byte Erasable Blocks
n SRAM-Compatible Write Interface
n User-Configurable x8 or x16 Operation
n Enhanced Data Protection Features
- Absolute Protection with Vpp=GND
- Flexible Block Locking
- Erase/Write Lockout during Power
Transitions
n Extended Cycling Capability
- 100,000 Block Erase Cycles
- 3.2 Million Block Erase Cycles/Chip
n Low Power Management
- Deep Power-Down Mode
- Automatic Power Savings Mode
Decreases ICC in Static Mode
n Automated Write and Erase
- Command User Interface
- Status Register
n Industry-Standard Packaging
- 56-Lead SSOP
n ETOXTM’ V Nonvolatile Flash
Technology
n CMOS Process
(P-type silicon substrate)
n Not designed or rated as radiation
hardened
SHARP’s LH28F160S5NS-L70 Flash memory with Smart 5 technology is a high-density, low-cost, nonvolatile,
read/write storage solution for a wide range of applications. Its symmetrically-blocked architecture, flexible voltage
snd extended cycling provide for highly flexible component suitable for resident flash arrays, SlMMs and memory
:ards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For
secure code storage applications, such as networking, where code is either directly executed out of flash or
downloaded to DRAM, the LH28F160S5NSL70 offers three levels of protection: absolute protection with V,, at
SND, selective hardware block locking, or flexible software block locking. These alternatives give designers
Jltimate control of their code security needs.
The LH28F160S5NS-L70 is conformed to the flash Scalable Command Set (SCS) and the Common Flash Interface
CFI) specification which enable universal and upgradable interface, enable the highest system/device data transfer
‘ates and minimize device and system-level implementation costs.
The LH28F160S5NS-L70 is manufactured on SHARP’s 0.35um ETOX TM* V process technology. It come in
ndustry-standard package: the 56-Lead SSOP, ideal for board constrained applications.
‘ETOX is a trademark of Intel Corporation.
Rev. 1.9

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LHF16KA4 전자부품, 판매, 대치품
SHARI=
. - LHF16KA4
5
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Table 2. Pin Descriptions
Symbol
Type Name and Function
ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are
internally latched during a write cycle.
A0420
INPUT
Ao: Byte Select Address. Not used in x16 mode(can be floated).
AI-AK Column Address. Selects 1 of 16 bit lines.
A5-A15: Row Address. Selects 1 of 2048 word lines.
Air+A20 : Block Address.
DATA INPUT/OUTPUTS:
DQo-DQ7:lnputs data and commands during CUI write cycles; outputs data during memory
array, status register, query, and identifier code read cycles. Data pins float to high-
C)QO-DC&5 OIUNTPPUUT/T
impedance when the chip is deselected or outputs are disabled. Data is internally latched
during a write cycle.
DQs-DQt5:lnputs data during CUI write cycles in xl 6 mode; outputs data during memory
array read cycles in xl 6 mode; not used for status register, query and identifier code read
mode. Data pins float to high-impedance when the chip is deselected, outputs are
disabled, or in x8 mode(Byte#=V,, ). Data is internally latched during a write cycle.
CE,#,
CE,#
INPUT
CHIP ENABLE: Activates the device’s control logic, input buffers decoders, and sense
amplifiers. Either CE,# or CE,# V,, deselects the device and reduces power consumption
to standby levels. Both CEr,# and CE,# must be V,, to select the devices.
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets
RP#
INPUT
internal automation. RP# V,, enables normal operation. When driven V,,, RP# inhibits
write operations which provides data protection during power transitions. Exit from deep
power-down sets the device to read array mode.
OE# INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WE#
INPUT
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
STS (RY/BY#): Indicates the status of the internal WSM. When configured in level mode
(default mode), it acts as a RY/BY# pin. When low, the WSM is performing an internal
OPEN operation (block erase, full chip erase, (multi) word/byte write or block lock-bit
STS DRAIN configuration). STS High Z indicates that the WSM is ready for new commands, block
OUTPUT erase is suspended, and (multi) word/byte write is inactive, (multi) word/byte write is
suspended or the device is in deep power-down mode. For alternate configurations of the
‘STATUS pin, see the Configuration command.
WP#
INPUT
WRITE PROTECT: Master control for block locking. When V,,, Locked blocks can not be
erased and programmed, and block lock-bits can not be set and reset.
BYTE#
INPUT
BYTE ENABLE: BYTE# V,, places device in x8 mode. All data is then input or output on
DQO-,, and DQs-,5 float. BYTE# V,, places the device in xl 6 mode , and turns off the A,
input buffer.
BLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE, BLOCK LOCK-
BIT CONFIGURATION POWER SUPPLY: For erasing array blocks, writing bytes or
VPP SUPPLY configuring block lock-bits. With V+V~~XL~, memory contents cannot be altered. Block
erase, full chip erase, (multi) word/byte write and block lock-bit configuration with an invalid
Vpp (see DC Characteristics) produce spurious results and should not be attempted.
DEVICE POWER SUPPLY: Internal detection configures the device for 5V operation. Do
VCC
SUPPLY
not float any power pins. With Vc,IV,kO, all write attempts to the flash memory are
inhibited. Device operations at invalid Voo voltage (see DC Characteristics) produce
spurious results and should not be attempted.
GND SUPPLY GROUND: Do not float any ground pins.
NC NO CONNECT: Lead is not internal connected; it may be driven or floated.
Rev. 1.9

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