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PDF LHF16KA9 Data sheet ( Hoja de datos )
| Número de pieza | LHF16KA9 | |
| Descripción | Flash Memory 16M (2MB bb 8/1MB bb 16) | |
| Fabricantes | Sharp Electrionic Components | |
| Logotipo |  |
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PRODUCT SPECIFICATIONS
®
Integrated Circuits Group
LH28F160S5T-L70A
Flash Memory
16M (2MB × 8/1MB × 16)
(Model No.: LHF16KA9)
Spec No.: EL127112A
Issue Date: August 29, 2000
1 page  
SHARP
. - LHFlGKA9
3
-1
1 INTRODUCTION
This datasheet contains LH28F160S5T-L70A
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications.
1.1 Product Overview
execute code from any other flash memory arrayI
location.
Individual block locking uses a combination of bit:
and WP#, Thirty-two block lock-bits, to lock ant
unlock blocks. Block lock-bits gate block erase, ful
chip erase and (multi) word/byte write operations
Block lock-bit configuration operations (Set BlocE
Lock-Bit and Clear Block Lock-Bits commands) se
and cleared block lock-bits.
The LH28F160S&T-L70A is a high-performance 16M-
bit Smart 5 Flash memory organized as
2MBx8/1 MBxl6. The 2MB of data is arranged in
thirty-two 64K-byte blocks which are individually
erasable, lockable, and unlockable in-system. The
memory map is shown in Figure 3.
i
Smart 5 technology provides a choice of V,, and
V,, combinations, as shown in Table 1, to meet
system performance and power expectations. 5V V,,
provides the highest read performance. V,, at 5V
eliminates the need for a separate 12V converter,
while V,,=5V maximizes erase and write
performance. In addition to flexible erase and
program voltages, the dedicated V,, pin gives
complete data protection when V,+V,,Lk.
Table 1. Vcc.and VP, Voltage Combinations
Offered by Smart 5 Technology
Vcr: Voltage
Vpp Voltage
5v
I
5v
,
The status register indicates when the WSM’s block
erase, full chip erase, (multi) word/byte write or block
lock-bit configuration operation is finished.
The STS output gives an additional indicator of WSM
activity by providing both a hardware signal of status
(versus software polling) and status masking
(interrupt masking for background block erase, for
example). Status polling using STS minimizes both
CPU overhead and system power consumption. STS
pin can be configured to different states using the
Configuration command. The STS pin defaults tc
RY/BY# operation. When low, STS indicates that the
WSM is performing a block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration.
STS-High Z indicates that the WSM is ready for a
new command, block erase is suspended and (multi)
word/byte write are inactive, (multi) word/byte write
are suspended, or the device is in deep power-down
mode. The other 3 alternate configurations are all
pulse mode for use as a system interrupt.
Internal VCC. and VW detection Circuitry
automatically configures the device for optimized
read and writeoperations.
A Command User Interface (CUI) serves as the
interface between the system processor and internal
operation of the device. A valid command sequence
written to the CUI initiates device automation. An
internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for
block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration operations.
A block erase operation erases one of the device’s
64K-byte blocks typically within 0.34s (5V Voo, 5V
V,,) independent of other blocks. Each block can be
independently erased 100,000 times (3.2 million
block erases per device). Block erase suspend mode
allows system software to suspend block erase to
read or write data from any other block.
The access time is 70ns (tAvQv) over the commercial
temperature range (0% to +7O”C) and Vc, supply
voltage range of 4.75V-5.25V. At lower Voc voltage,
the access time is 80ns (45V-55V).
The Automatic Power Savings (APS) feature
substantially reduces active current when the device
is in static mode (addresses not switching). In APS
m-ode, the typical lCCR current is 1 mA at 5V V,,.
When either CE,# or CE,#, and RP# pins are at Vcc,
the I,, CMOS standby mode is enabled. When the
RP# pin is at GND, deep power-down mode is
enabled which minimizes power consumption and
provides write protection during reset. A reset time
(tPHav) is required from RP# switching high until
outputs are valid. Likewise, the device has a wake
time (tpHEL) from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset and
the status register is cleared.
A word/byte write is performed in byte increments
typically within 9.24us (5V Vcc, 5V Vpp). A multi
word/byte write has high speed write performance of
2uslbyte (5V Vcc, 5V V,,). (Multi) Word/byte write
suspend mode enables the system to read data or
The device is available in 56-Lead TSOP (Thin Small
Outline Package, 1.2 mm thick). Pinout is shown in
Figure 2.
Rev. 1.9
5 Page 
SHARI=
.-
Mode
Read
Output Disable
Standby
Deep Power-Down
Read Identifier
Codes
Query
Write
LHFlGKA9
9
--
1 Notes
1 1 r&3,9
3
3
4
9
9
3,7,&g
Table 3. Bus Operations(BYTE#=V,,)
1 RP# 1 CEd 1 CEd 1 OE# I WE#
1 vlH
I VII
I VII
I VII
! VIH
V,,-, V,, V,, V,,-, V,H
VI, VI,
VI, $H VI,
X
II V,H
V,, X X X
X
X
VI, VI, VI, VI, vlH
vlH VI, VI, VI, vlH
v,H V,, V,, v,H V,,
I Address 1 VP,,
! X 1X
XX
XX
X
See
Figure 4
See Table
7-11
X
X
’
x
X
I DQ,,,li I STS
b-ml
High Z
X
X
High Z X
High Z High Z
Note 5 High Z
Note 6 High Z
D,N X
Mode
Read .
Outputbisable
Notes
1,2,3,9
3
Table 3.1. Bus Operations(BYTE#=V
RP# CEn# CE,# OE# WE#
v,,, V,, V,, V,, v,,,
V,M v,,
V,, V,,-j V,H
,)
Address
X
X
VP,, DQ&,
X DolIT
X HighZ
STS
X
X
Standby
VI, vlH
3 vlH vlH VI,
XX
X
X High Z X
v,, v,,,
Deep Power-Down
4 v,, X X X X
X
X High Z High Z
Read Identifier
Codes
9 ‘1,
YL
YL
YL
‘1,
See
Figure 4
’
Note 5 High Z
Query
9 VI,
VI,
VI,
VI,
See Table x
vlH 7-11
Note 6 High Z
Write
3,7,&g v,H
V,,
V,,
v,,,
V,,
X
X D,N X
NOTES:
1. Refer to DC Characteristics. When VpplVppLK, memory contents can be read, but not altered.
2. X can be VIL or V,H for control pins and addresses, and VP,,, or VP,,+, for V,,. See DC Characteristics for
VP,,, and VP,,, voltages.
3. STS is VoL (if configured to RY/BY# mode) when the WSM is executing internal block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration algorithms. It isfloated during when the WSM is not busy,
in block erase suspend mode with (multi) word/byte write inactive, (multi) word/byte write suspend mode, or
deep power;down mode.
4. RP# at GNDlt0.2V ensures the lowest deep power-down current.
5. See Section 4.2 for read identifier code data.
6. See Section 4.5 for query data.
7. Command writes involving block erase, full chip erase, (multi) word/byte write or block lock-bit configuration are
reliably executed when VPP=VPr+,1and Vcc=Vcc,,2.
8. Refer to Table 4 for valid D,, during a write operation.
9. Don’t use the timing both OE# and WE# are VI,.
Rev. 1.9
11 Page | ||
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