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PDF OM5926HN Data sheet ( Hoja de datos )
| Número de pieza | OM5926HN | |
| Descripción | I2C-bus Sim Card Interface | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
www.DataSheet4U.com
OM5926HN
I2C-bus SIM card interface
Product specification
2003 Feb 19
1 page  
Philips Semiconductors
I2C-bus SIM card interface
6 BLOCK DIAGRAM
Product specification
OM5926HN
www.DataSheet4U.com
handbook, full pagewidth
VUP 9
PGND 4
100 nF
VDDP
100 nF
2.2 µF
S3 S4 S1 S2
5 7386
DC / DC
CONVERTER
OM5926HN
VDDS
100 nF
15
SIMMERRN
SUPPLY
SUPERVISOR
16 DEL
10 nF
VCC
200
nF
13
RST
14
I/O 10
ANALOG
DRIVERS
AND
PROTECTIONS
PRES
SEQUENCER
18
OSCILLATOR
SAD0
SAD1
I 2C - BUS
AND
REGISTERS
19
20
2
CLOCK
COUNTER
17
20 kΩ
pull-up
to VDDI
VDDI
SDA
SCL
PWROFF
SIMI/O
CLK
12
11
SGND
CLOCK
CIRCUITRY
1
MGU806
SIMCLK
2003 Feb 19
Fig.1 Block diagram.
5
5 Page 
Philips Semiconductors
I2C-bus SIM card interface
Product specification
OM5926HN
8.7.1 ACTIVATION SEQUENCE
Figure 4 shows the activation sequence. When the card is
inactive, VCC, CLK, RST and I/O are LOW, with
low-impedance with respect to ground. The DC-to-DC
converter is stopped. SIMI/O is pulled HIGH at VDDI via the
20 kΩ pull-up resistor. When all conditions are met (supply
voltage, card present, no hardware problems), the
www.DataShemeti4cUro.ccoomntroller may initiate an activation sequence by
setting the START bit to logic 1 (t0) via the I2C-bus:
1. The DC-to-DC converter is started (t1).
2. VCC starts rising from 0 to 3 V or 0 to 5 V, according to
the state of the 3 V/5 VN control bit, with a controlled
rise time of 0.17 V/µs typically (t2).
3. I/O buffer is enabled in reception mode (t3).
4. CLK is sent to the card reader with RST = LOW, and
the count of 41928 CLK pulses is started (t4 = tact).
5. If a start bit is detected on I/O, the clock counter is
stopped with RST = LOW. If not, RST = HIGH, and a
new count of 41928 CLK pulses is started (t5).
If a start bit is detected on I/O and the clock counter is
stopped with RST = HIGH, the card session may continue.
If not, the MUTE bit is set in the Status register. The
microcontroller may initiate a deactivation sequence by
setting the START bit to logic 0.
If a start bit is detected during the first 200 CLK pulses of
each count slot, then it will not be taken into account. If a
start bit is detected during 200 and 352 CLK pulses of
each slot, then bit EARLY is set in the status register. The
microcontroller may initiate a deactivation sequence by
setting the START bit to logic 0.
The sequencer is clocked by 1⁄64fosc which leads to a time
interval T of 25 µs typically. Thus t1 = 0 to 1⁄2 T;
t2 = t1 + 3⁄2 T; t3 = t1 + 7⁄2 T; t4 = t1 + 4 T and t5 depends on
the SIMCLK frequency.
handbook, full pagewidth
START
VCC
I/O
CLK
RST
,
,
SIMI/O
t0, t1 t2
t3 t4 (= tact)
t5
the 200 first CLK pulses are masked
MGR437
Answer To Reset (ATR) begin
Fig.4 Activation sequence.
2003 Feb 19
11
11 Page | ||
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| PDF Descargar | [ Datasheet OM5926HN.PDF ] | |
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