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CS5504 데이터시트 PDF




Cirrus Logic에서 제조한 전자 부품 CS5504은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 CS5504 자료 제공

부품번호 CS5504 기능
기능 20-Bit A/D Converter
제조업체 Cirrus Logic
로고 Cirrus Logic 로고


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CS5504 데이터시트, 핀배열, 회로
CCDCSB5S55550504044
EvaluLLaotoiwown-PpBoowowaeerrd,,22f0o0-r-BbCiittSAA5/5/DD04CCAoon/nDveCrotenrverter
Features
l Delta-sigma A/D Converter
- 20-bit, No Missing Codes
- Linearity Error: ±0.0007%FS
l 2 Differential Inputs
- Pin-selectable Unipolar/Bipolar Ranges
www.DataSheet4U- .cComommon Mode Rejection
105 dB @ dc
120 dB @ 50, 60 Hz
l Either 5V or 3.3V Digital Interface
l On-chip Self-calibration Circuitry
l Output Update Rates up to 200/Sps
l Low Power Consumption: 4.4 mW
Description
The CS5504 is a 2-channel, fully differential 20-bit, seri-
al-output CMOS A/D converter. The CS5504 uses
charge-balanced (delta-sigma) techniques to provide a
low cost, high-resolution measurement at output word
rates up to 200 samples per second.
The on-chip digital filter offers superior line rejection at
50 Hz and 60 Hz when the device is operated from a
32.768 kHz clock (output word rate = 20 Sps).
The CS5504 has on-chip self-calibration circuitry which
can be initiated at any time or temperature to ensure
minimum offset and full-scale errors.
Low power, high-resolution and small package size
make the CS5504 an ideal solution for loop-powered
transmitters, panel meters, weigh scales and battery-
powered instruments.
ORDERING INFORMATION
See page 23.
CS5504-BS -40° to +85° C 20-pin SOIC
I
VREF+
12
VREF-
13
VA+ VA- DGND VD+
14 15
16 17
AIN1+
AIN1-
8
10
AIN2+
AIN2-
9
11
MUX
4th-Order
Delta-Sigma
Modulator
Digital
Filter
Serial
Interface
Logic
2
CS
18 SCLK
19
SDATA
20
DRDY
A0 1
Calibration SRAM
Calibration µC
OSC
3 56
CONV XIN XOUT
4 CAL
7 BP/UP
Cirrus Logic, Inc.
PCh.rtOtyps.:/tB/awol wxSw1e7m.c8iir4cr7uo,snA.dcuousmctitno,rTPerxoadsu7c8ts76D0ivision
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
Copyright © CirrCuospLyoriggich,t I©ncC. i2rr0u0s5Logic, Inc. 1997
(All Rights Rese(rAvell dR)ights Reserved)
MAUARG ‘905
DSA1U2G6F1025
DS126DB12




CS5504 pdf, 반도체, 판매, 대치품
CS5504
CS5504
5V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ± 10%;
VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)
Parameter
Symbol Min Typ Max Units
Master Clock Frequency
Internal Oscillator
External Clock
XIN 30.0 32.768 53.0 kHz
fclk 30
- 330 kHz
Master Clock Duty Cycle
40 - 60 %
Rise Times:
Any Digital Input (Note 9)
Any Digital Output
trise
-
-
- 1.0 µs
50 - ns
Fall Times:
www.DataSheet4U.com
Any Digital Input (Note 9)
Any Digital Output
tfall
-
-
- 1.0 µs
20 - ns
Start-Up
Power-On Reset Period
(Note 10) tres
-
10
- ms
Oscillator Start-up Time
XTAL = 32.768 kHz (Note 11) tosu
-
500
- ms
Wake-up Period
(Note 12) twup
- 1800/fclk -
s
Calibration
CONV Pulse Width (CAL=1)
(Note 13) tccw
100
-
- ns
CONV and CAL High to Start of Calibration
tscl -
- 2/fclk+200 ns
Start of Calibration to End of Calibration
tcal - 3246/fclk - s
Conversion
Set Up Time
A0 to CONV High
tsac 50
-
- ns
Hold Time
A0 after CONV High
thca 100
-
- ns
CONV Pulse Width
tcpw 100
-
- ns
CONV High to Start of Conversion
tscn -
- 2/fclk+200 ns
Set Up Time
BP/UP stable prior to DRDY falling tbus
82/fclk
-
-s
Hold Time
BP/UP stable after DRDY falls tbuh
0
-
- ns
Start of Conversion to End of Conversion
(Note 14) tcon
- 1624/fclk -
s
Notes: 9. Specified using 10% and 90% points on waveform of interest.
10. An internal power-on-reset is activated whenever power is applied to the device.
11. Oscillator start-up time varies with the crystal parameters. This specification does not apply when
using an external clock source.
12. The wake-up period begins once the oscillator starts; or when using an external fclk, after the
power-on reset time elapses.
13. Calibration can also be initiated by pulsing CAL high while CONV=1.
14. Conversion time will be 1622/fclk if CONV remains high continuously.
4 DS126F21

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CS5504 전자부품, 판매, 대치품
CS5504
CS5504
5V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ± 10%;
VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)
Parameter
Symbol Min Typ Max Units
Serial Clock
fsclk 0
- 2.5 MHz
Serial Clock
Pulse Width High
Pulse Width Low
tph 200
tpl 200
-
-
- ns
- ns
Access Time:
CS Low to data valid (Note 15) tcsd
-
60 200 ns
Maximum Delay Time:
(Note 16)
SCLK falling to new SDATA bit tdd - 150 310 ns
www.DataSheet4U.com
Output Float Delay:
CS high to output Hi-Z (Note 17) tfd1
-
60 150 ns
SCLK falling to Hi-Z tfd2 - 160 300 ns
Notes: 15. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high
for 2 clock cycles. The propagation delay time may be as great as 2 fclk cycles plus 200 ns. To
guarantee proper clocking of SDATA when using asynchronous CS, SCLK should not be taken high
sooner than 2/fclk + 200 ns after CS goes low.
16. SDATA transitions on the falling edge of SCLK. Note that a rising SCLK must occur to enable the
serial port shifting mechanism before falling edges can be recognized.
17. If CS is returned high before all data bits are output, the SDATA output will complete the current data
bit and then go to high impedance.
3.3V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ± 10%; VD+ = 3.3V ±
5%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)
Parameter
Symbol Min Typ Max Units
Serial Clock
fsclk 0
- 1.25 MHz
Serial Clock
Pulse Width High
Pulse Width Low
tph 200
tpl 200
-
-
- ns
- ns
Access Time:
CS Low to data valid (Note 15) tcsd - 100 200 ns
Maximum Delay Time:
(Note 16)
SCLK falling to new SDATA bit tdd - 400 600 ns
Output Float Delay:
CS high to output Hi-Z (Note 17) tfd1
-
70 150 ns
SCLK falling to Hi-Z tfd2 - 320 500 ns
DS126F12
7

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