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PDF CS5511 Data sheet ( Hoja de datos )
| Número de pieza | CS5511 | |
| Descripción | (CS5510 - CS5513) 8-pin Sigma-Delta ADC | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS5510/11/12/13
16-bit and 20-bit, 8-pin ∆Σ ADC
Features
z Delta-sigma Analog-to-digital Converter
– Linearity Error: 0.0015% FS
– Noise-free Resolution: Up to 17 Bits
z Differential Bipolar Analog Inputs
www.DataSheezt4UV.cRoEmF Input Range from 250 mV to 5 V
z 50/60 Hz Simultaneous Rejection
(CS5510/12)
z 16 to 326 Sps Output Word Rate
z On-chip Oscillator (CS5511/13)
z Power Supply Configurations:
– V+ = 5 V, V- = 0 V
– Multiple Dual-supply Arrangements
z Low Power Consumption
– Normal Mode, 2.5 mW
– Sleep Mode, 10 µW
z Low-cost, Compact, 8-pin Package
z Lead-free Device Package Options
General Description
The CS5510/11/12/13 are low-cost, easy-to-use, ∆Σ an-
alog-to-digital converters (ADCs) which use charge-
balance techniques to achieve 16-bit (CS5510/11) and
20-bit (CS5512/13) performance. The ADCs are avail-
able in a space-efficient, 8-pin SOIC package and are
optimized for measuring signals in weigh scale, process
control, and other industrial applications.
To accommodate these applications, the ADCs include
a fourth-order ∆Σ modulator and a digital filter. When
configured with an external master clock of 32.768 kHz,
the filter in the CS5510/12 provides better than 80 dB of
simultaneous 50 and 60 Hz line rejection, and outputs
conversion words at 53.5 Sps. The CS5511/13 include
an on-chip oscillator which eliminates the need for an ex-
ternal clock source.
Low-power, flexible supply configurations, compact pi-
nout, and ease of use make these products ideal
solutions for cost-conscience and space-constrained
applications.
ORDERING INFORMATION
See page 23.
AIN+
AIN-
VREF
1X
~0.8X
http://www.cirrus.com
V+
Differential
4th-order
Delta-sigma
Modulator
Digital Filter
Output
Control
Logic
CS
SDO
SCLK
Oscillator
(CS5511/13 only)
Clock
Gen.
(CS5510/12 only)
V-
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
AUG ‘05
DS337F3
1 page  
CS5510/11/12/13
ANALOG CHARACTERISTICS (Continued)
Parameter
Voltage Reference Input
Range
{(VREF) - (V-)}
Input Capacitance
CVF current
Power Supplies
Supply Voltages
{(V+) - (V-)}
DC Power Supply Currents
www.DataSheet4U.com
IV+
IV-
Power Consumption
Power Supply Rejection
Sleep
dc Positive Supply
dc Negative Supply
Min Typ
Max
Unit
(Note 8) 0.250 2.5 (V+) - (V-) V
-7
- pF
-6
- nA
(Note 9)
CS5510
CS5511
CS5512
CS5513
CS5510
CS5511
CS5512
CS5513
(Note 10)
CS5510
CS5511
CS5512
CS5513
(Note 11)
4.75
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
275
290
360
385
275
290
360
385
1.4
1.5
1.8
1.9
10
85
85
5.25 V
360 µA
380 µA
470 µA
500 µA
360 µA
380 µA
470 µA
500 µA
1.9 mW
2.0 mW
2.5 mW
2.7 mW
- µW
- dB
- dB
Notes: 8.
9.
10.
11.
VREF is referenced to V- and must be less than or equal to V+.
Due to current through the CS pin, IV+ and IV- may not always be the same value.
All outputs unloaded. All inputs CMOS levels (> (V+ - 0.6 V) or < (V- + 0.6 V)).
CS must be inactive (logic high) during sleep to meet this power specification.
DIGITAL CHARACTERISTICS
(TA = 25° C; V+ = 5 V ±5%; V- = 0 V) (See Notes 1 and 12.)
Parameter
Symbol Min Typ
Max
Unit
High-Level Input Voltage:
Low-Level Input Voltage:
Input Current:
High-Level Output Voltage:
Low-Level Output Voltage:
Input Leakage Current
3-State Leakage Current
CS and SCLK
(Note 13) CS
SCLK
(Note 14) CS
SDO, Isource = 5.0mA
(Note 14) SDO, Isink = 1.0mA
SCLK
SCLK
VIH
CSLow
VIL
ICS
VOH
VOL
Iin
IOZ
V+ - 0.45 -
-
--
--
--
VL1
VL1
1.0
(V+) - 0.6 -
-
- - (CSLow) + 0.6
- ±0.015
±10
--
±10
V
V
V
mA
V
V
µA
µA
Notes: 12.
13.
14.
All measurements performed under static conditions.
VL1 is 0.5 (V+ - V-) + 0.6 V + V-.
The CS signal provides the sink current path for the SDO pin when CS is low. The external drive logic
to CS, therefore, must be able to handle the logic-low current drive levels for all devices attached to
SDO. The voltage specified for SDO is relative to CSLow. See Section 2.3.1, “Digital Logic Levels” and
Figure 11 for more details.
DS337F3
5
5 Page 
CS5510/11/12/13
CS5512/13. The CS5510/11 follow the same
curve, but are limited to 16 bits of resolution. Note
that the reference voltage should not be estab-
lished prior to having the supply voltages on the V+
and V- pins.
2.2.1 Voltage Reference Input Model
Figure 5 illustrates the input model for the VREF
pin. It includes a coarse/fine charge buffer which
reduces the dynamic current demand of the exter-
www.DataSheet4U.com
17
16
15
14
13
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VREF (V)
Figure 4. CS5512/13 Measured Noise-Free Bits vs.
VREF.
nal reference. Typical CVF (sampling) current is
about 6 nA (See Figure 5).
The nominal input span of the converter is defined
to be a bipolar span equal to ±(VREF - V-)*(0.80
±0.08).
2.3 Power Supply Arrangements
The CS5510/11/12/13 are designed to operate
from single or dual supplies. Figure 6 illustrates the
CS5510/11/12/13 connected with a single +5 V
supply to measure differential inputs relative to a
common mode of 2.5 V. Figure 7 illustrates the
CS5510/11/12/13 connected with ±2.5 V analog
supplies to measure ground-referenced, bipolar
signals. It is not necessary that the dual supples on
the ADCs be balanced, however, they must sum to
five volts. Figure 8 illustrates the ADCs configured
with V+ = +3.3 V and V- = -1.7 V, accommodating
a +3.3 V digital supply.
2.3.1 Digital Logic Levels
The many power supply configurations available in
the CS5510/11/12/13 allow for a wide range of dig-
ital logic levels. The logic-high input and output lev-
els are determined by the V+ pin. The logic-low
output on SDO is referenced to and driven by the
current logic-low voltage on CS. Since the
CS5510/11/12/13 do not include a dedicated
DS337F3
VREF
Vo s ≤ 2 5 mV
i n = f Vo s C
φ
1
Fine
φ2 Coarse
C = 7pF
f = 32.768 kHz
Figure 5. Input model for VREF pin.
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet CS5511.PDF ] | |
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