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PDF CS5542 Data sheet ( Hoja de datos )
| Número de pieza | CS5542 | |
| Descripción | (CS5542 / CS5543) Multi-Channel DS ADC Chip Set | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CS5542 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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CS5542
CS5543
22-Bit, Multi-Channel ∆Σ ADC Chip Set
Features
l Delta-Sigma Architecture:
- 5th Order Modulator
- 22-Bit Resolution
l dc Accuracy (fBW = 250Hz):
- Integral Linearity: ±0.001 % F.S.
www.DataSheet4U- .cDomifferential Linearity: ±0.5 LSBs
- RMS Noise: 1.1 pARMS
l Pin Selectable Input Range:
- ±400 nA to ±2.5 µA Full Scale
l 8-Channel Digital FIR Filter
l Self-calibration of Offset and Gain
l Low Power: 50 mW /ch for 8-ch system
Description
The CS5542 / CS5543 chip set is designed to be a com-
plete current measurement data acquisition system.
The CS5542 is a 22-Bit, 2-channel, 5th-order delta sig-
ma modulator. The CS5543 is a monolithic CMOS, 8-
channel digital FIR filter designed to be used with up to
four CS5542’s forming an 8-channel system. The com-
plete system is capable of cascading up to 1024
channels.
The system supports 22-bit measurement resolution
with output conversion rates up to 1 kHz per channel.
JTAG boundary-scan capability is available to facilitate
self-test at the system level.
Potential applications for the CS5542/CS5543 system
are environmental monitoring, process control systems,
color sensing, light measurement, chemical analyzers
and photo-diode transducer applications.
ORDERING INFORMATION
CS5542-KL 0 to 70°C
CS5543-KL 0 to 70°C
28-pin PLCC
28-pin PLCC
VD1+GND1VD2+GND2VD3+GND3
REFGNDL
INL
ICAL
INR
REFGNDR
VA+ VA- GNDL VD+ DGND
5th Order
Delta-Sigma
Modulator
Left
Channel
ICAL Bias
MUX Regulator
5th Order
Delta-Sigma
Modulator
Right
Channel
Calibra-
tion
and
Digital
Control
Logic
VREF+ VREF- GNDR SEL0SEL1
CS5542
CAPSIZE
MCLK
FSYNC
PDN
C[2.0]
CAL[1:0]
3
2
Control/Sequencing
CAPSIZE
TCK
TMS
TDI
Test
Access
TDO Port
PDN
MCLK
FSYNC
CAL[1:0]
MDATA
[3:0]
4
MDATA[3:0]
C[2:0]
DATACLK
FRAME
Serial I/O
CS5543
3 DMODE[2:0]
RST
CLKIN
FEGAIN
OE
4 DATSEL[3:0]
4 DATAIN[3:0]
4
DATAOUT
[3:0]
Preliminary Product Information
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 1997
(All Rights Reserved)
SEP ‘96
DS109PP2
1
1 page  
CS5542 CS5543
DATACLK
TCK, CLKIN
FRAME
DATAIN [3:0]
DATAOUT [3:0]
www.DataSheet4DUM.cOoDmE [2:0],
DATSEL[3:0],
JTAG pins,
OE, FEGAIN
MCLK
19
FSYNC
3
11
13
14
20
21
22
9
15
valid data
valid data
19
4
16 17
18
CS5542/CS5543 System Timing Diagram
Output Word Cycle
FRAME
CLKIN
DATACLK
DATAOUT [3:0]
N-1
N
1 Filter Output Time
N+1
N-3
N-2
N+2
N-1
N+3
N
Expanded inter-view timing
FRAME
CLKIN
DATACLK
DATAOUT [3:0]
parity bit from
"most remote" channel
(end of Frame N-3)
Multi-Frame System Timing Diagram
DS109PP2
sign bit from
"nearest" channel
(beginning of Frame N-2)
5
5 Page 
CS5542 CS5543
INL0
INR0
ICAL
www.DataSheet4U.com
INL1
INR1
INL2
INR2
INL3
INR3
INL
INR
ICAL
MDATA[3:0]
C[2:0]
CAL[1:0]
FSYNC
CS5542 MCLK
PDN
CAPSIZE
SEL1 DGND
SEL0 DGND
INL
INR
ICAL
MDATA[3:0]
C[2:0]
CAL[1:0]
FSYNC
CS5542 MCLK
PDN
CAPSIZE
SEL1 DGND
SEL0 VD+
INL
INR
ICAL
MDATA[3:0]
C[2:0]
CAL[1:0]
FSYNC
CS5542 MCLK
PDN
CAPSIZE
SEL1 VD+
SEL0 DGND
INL
INR
ICAL
MDATA[3:0]
C[2:0]
CAL[1:0]
FSYNC
CS5542 MCLK
PDN
CAPSIZE
SEL1 VD+
SEL0 VD+
CS5543
CAPS
PDN
MCLK
FSYNC
CAL[1:0]
C[2:0]
MDATA[3:0]
OE
FEGAIN
FRAME
DATCLK
CLKIN
DATAOUT[3:0]
DATAIN[3:0]
DATSEL[3:0]
DMODE[2:0]
RST
TCK
TMS
TDI
TDO
Supplies omitted for clarity
OE
FEGAIN
FRAME
DATCLK
CLKIN
DATAOUT[3:0]
DATAIN[3:0]
DATSEL[3:0]
DMODE[2:0]
RST
TCK
TMS
TDI
TDO
Figure 2. Typical 8-channel Connection Diagram
DS109PP2
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS5542.PDF ] | |
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