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PDF CS5560 Data sheet ( Hoja de datos )
| Número de pieza | CS5560 | |
| Descripción | High-throughput ADC | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CS5560 (archivo pdf) en la parte inferior de esta página. Total 32 Páginas | ||
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7/31/07
CS5560
±2.5 V / 5 V, 50 kSps, 24-bit, High-throughput ∆Σ ADC
Features & Description
Differential Analog Input
On-chip Buffers for High Input Impedance
Conversion Time = 20 µS
Settles in One Conversion
www.DataSheet4U.cLoimnearity Error = 0.0007%
Signal-to-Noise = 110 dB
24 Bits, No Missing Codes
Self-calibration:
- Maintains accuracy over time & temperature.
Simple three/four-wire serial interface
Power Supply Configurations:
- Analog: +5V/GND; IO: +1.8V to +3.3V
- Analog: ±2.5V; IO: +1.8V to +3.3V
Power Consumption:
- ADC Input Buffers On: 85 mW
- ADC Input Buffers Off: 70 mW
General Description
The CS5560 is a single-channel, 24-bit analog-to-digital
converter capable of 50 kSps conversion rate. The input
accepts a fully differential analog input signal. On-chip
buffers provide high input impedance for both the AIN in-
puts and the VREF+ input. This significantly reduces the
drive requirements of signal sources and reduces errors
due to source impedances. The CS5560 is a delta-sigma
converter capable of switching multiple input channels at
a high rate with no loss in throughput. The ADC uses a
low-latency digital filter architecture. The filter is designed
for fast settling and settles to full accuracy in one conver-
sion. The converter's 24-bit data output is in serial form,
with the serial port acting as either a master or a slave. The
converter is designed to support bipolar, ground-refer-
enced signals when operated from ±2.5V analog supplies.
The CS5560 uses self-calibration to achieve low offset and
gain errors. The converter achieves a S/N of 110 dB. Lin-
earity is ±0.0007% of full scale.
The converter can operate from an analog supply of 0-5V
or from ±2.5V. The digital interface supports standard log-
ic operating from 1.8, 2.5, or 3.3 V.
ORDERING INFORMATION:
See Ordering Information on page 32.
V1+ V2+
VL
VREF+
VREF-
AIN+
AIN-
ADC
CS5560
DIGITAL
FILTER
LOGIC
SERIAL
INTERFACE
SMODE
CS
SCLK
SDI
SDO
RDY
BUFEN
OSC/CLOCK
GENERATOR
CALIBRATION
MICROCONTROLLER
SLEEP
RST
CONV
CAL
BP/UP
MCLK
V1- V2-
DCR
VLR
Advance Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2007
(All Rights Reserved)
AUG ‘07
DS713A5
1 page  
7/31/07
CS5560
ANALOG CHARACTERISTICS (CONTINUED) TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- =
V2- = -2.5 V, ±5%; VL -VLR = 3.3 V, ±5%; VREF = (VREF+) - (VREF-) = 4.096V; MCLK = 16 MHz; SMODE = VL.;
BUFEN = V1+ unless otherwise stated. Connected per Figure 7.
Parameter
Analog Input
Analog Input Range
Unipolar
Bipolar
Input Capacitance
CVF Current (Note 5)
www.DataSheet4U.com
AIN Buffer On (BUFEN = V+)
AIN Buffer Off (BUFEN = V-)
ACOM
Voltage Reference Input
Voltage Reference Input Range
(VREF+) – (VREF-)
(Note 6)
Input Capacitance
CVF Current
VREF+ Buffer On (BUFEN = V+)
VREF+ Buffer Off (BUFEN = V-)
VREF-
Power Supplies
DC Power Supply Currents
Power Consumption
IV1
IV2
IVL
Normal Operation Buffers On
Buffers Off
Power Supply Rejection
(Note 7) V1+ , V2+ Supplies
V1-, V2- Supplies
Min
-
-
-
-
2.4
-
-
-
-
-
-
-
-
-
90
90
Typ Max
0 to +VREF
±VREF
10
600
130
130
-
-
-
-
4.096
10
3
1
1
-
-
-
85
70
110
110
4.2
-
-
-
-
18
1.8
0.5
105
90
-
-
Unit
V
V
pF
nA
µA
µA
V
pF
µA
mA
mA
mA
mA
mA
mW
mW
dB
dB
5. Measured using an input signal of 1 V DC.
6. For optimum performance, VREF+ should always be less than (V+) - 0.2 volts to prevent saturation of the VREF+ input buffer.
7. Tested with 100 mVP-P on any supply up to 1 kHz. V1+ and V2+ supplies at the same voltage potential, V1- and V2- supplies at
the same voltage potential.
DS713A5
5
5 Page 
7/31/07
CS5560
SWITCHING CHARACTERISTICS (CONTINUED)
TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;
VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%
Input levels: Logic 0 = 0V; Logic 1 = VD+; CL = 15 pF.
Parameter
Symbol Min Typ Max
Calibration Register Write Timing
Data setup time before SCLK rising
t29 10
-
-
Data hold time after SCLK rising
t30 10
-
-
SCLK rising to CS rising
www.DataSheet4U.com
t31 10
-
-
17. SDO will be high impedance when CS is high. In some systems it may require a pull-down resister.
Unit
ns
ns
ns
CS
SCLK(i)
SDI
t31
t29 t30
MSB
Command Time
8 SCLKs
LSB MSB
LSB
Data Time
24 SCLKs
Figure 5. SEC Mode - Write Timing (Not to Scale)
DS713A5
11
11 Page | ||
| Páginas | Total 32 Páginas | |
| PDF Descargar | [ Datasheet CS5560.PDF ] | |
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