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PDF CS5571 Data sheet ( Hoja de datos )
| Número de pieza | CS5571 | |
| Descripción | High-throughput ADC | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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6/25/07
14:12
CS5571
±2.5 V / 5 V, 100 kSps, 16-bit, High-throughput ∆Σ ADC
Features & Description
Single-ended Analog Input
On-chip Buffers for High Input Impedance
Conversion Time = 10 µS
Settles in One Conversion
www.DataSheet4U.cLoimnearity Error = 0.0007%
Signal-to-Noise = 92 dB
S/(N + D) = 91 dB
DNL = ±0.1 LSB Max.
Self-calibration:
- Maintains accuracy over time & temperature.
Simple three/four-wire serial interface
Power Supply Configurations:
- Analog: +5V/GND; IO: +1.8V to +3.3V
- Analog: ±2.5V; IO: +1.8V to +3.3V
Power Consumption:
- ADC Input Buffers On: 85 mW
- ADC Input Buffers Off: 60 mW
General Description
The CS5571 is a single-channel, 16-bit analog-to-digital
converter capable of 100 kSps conversion rate. The input
accepts a single-ended analog input signal. On-chip buff-
ers provide high input impedance for both the AIN input
and the VREF+ input. This significantly reduces the drive
requirements of signal sources and reduces errors due to
source impedances. The CS5571 is a delta-sigma convert-
er capable of switching multiple input channels at a high
rate with no loss in throughput. The ADC uses a low-laten-
cy digital filter architecture. The filter is designed for fast
settling and settles to full accuracy in one conversion. The
converter's 16-bit data output is in serial format, with the
serial port acting as either a master or a slave. The convert-
er is designed to support bipolar, ground-referenced
signals when operated from ±2.5V analog supplies.
The CS5571 uses self-calibration to achieve low offset and
gain errors. The converter achieves a S/N of 92 dB. Linear-
ity is 0.0007% of full scale.
The converter can operate from an analog supply of 0-5V
or from ±2.5V. The digital interface supports standard logic
operating from 1.8, 2.5, or 3.3 V.
ORDERING INFORMATION:
See Ordering Information on page 31.
V1+ V2+
VL
VREF+
VREF-
AIN
ACOM
ADC
CS5571
DIGITAL
FILTER
LOGIC
SERIAL
INTERFACE
SMODE
CS
SCLK
SDO
RDY
BUFEN
OSC/CLOCK
GENERATOR
CALIBRATION
MICROCONTROLLER
DITHER
RST
CONV
CAL
BP/UP
MCLK
V1- V2-
TST
DCR
VLR
Advance Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2007
(All Rights Reserved)
JUN ‘07
DS768A5
1 page  
6/25/07
14:12
CS5571
ANALOG CHARACTERISTICS (CONTINUED) TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- =
V2- = -2.5 V, ±5%; VL -VLR = 3.3 V, ±5%; VREF = (VREF+) - (VREF-) = 4.096V; MCLK = 16 MHz; SMODE = VL.
DITHER = VL unless otherwise stated; BUFEN = V1+ unless otherwise stated. Connected per Figure 5.
Parameter
Analog Input
Analog Input Range
Unipolar
Bipolar
Input Capacitance
CVF Current (Note 6)
www.DataSheet4U.com
AIN Buffer On (BUFEN = V+)
AIN Buffer Off (BUFEN = V-)
ACOM
Voltage Reference Input
Voltage Reference Input Range
(VREF+) – (VREF-)
(Note 7)
Input Capacitance
CVF Current
VREF+ Buffer On (BUFEN = V+)
VREF+ Buffer Off (BUFEN = V-)
VREF-
Power Supplies
DC Power Supply Currents
Power Consumption
IV1
IV2
IVL
Normal Operation Buffers On
Buffers Off
Power Supply Rejection
(Note 8) V1+ , V2+ Supplies
V1-, V2- Supplies
Min
-
-
-
-
2.4
-
-
-
-
-
-
-
-
-
90
90
Typ Max
0 to +VREF / 2
±VREF / 2
10
600
130
130
-
-
-
-
4.096
10
3
1
1
-
-
-
85
60
110
110
4.2
-
-
-
-
18
1.8
0.5
105
90
-
-
Unit
V
V
pF
nA
µA
µA
V
pF
µA
mA
mA
mA
mA
mA
mW
mW
dB
dB
6. Measured using an input signal of 1 V DC.
7. For optimum performance, VREF+ should always be less than (V+) - 0.2 volts to prevent saturation of the VREF+ input buffer.
8. Tested with 100 mVP-P on any supply up to 1 kHz. V1+ and V2+ supplies at the same voltage potential, V1- and V2- supplies at
the same voltage potential.
DS768A5
5
5 Page 
6/25/07
14:12
CS5571
GUARANTEED LOGIC LEVELS
TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;
VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%
Input levels: Logic 0 = 0V; Logic 1 = VL; CL = 15 pF.
Parameter
Logic Inputs
www.DataSheet4U.cMominimum High-level Input Voltage:
Maximum Low-level Input Voltage:
Logic Outputs
Minimum High-level Output Voltage:
Maximum Low-level Output Voltage:
Sym VL
Guaranteed Limits
Min Typ Max Unit Conditions
3.3 1.9
VIH 2.5 1.6
1.8 1.2
3.3
VIL 2.5
1.8
V
1.1
0.95 V
0.6
3.3 2.9
VOH 2.5
2.1
1.8 1.65
3.3
VOL 2.5
1.8
V
0.36
0.36
0.44
V
IOH = -2 mA
IOH = -2 mA
DS768A5
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS5571.PDF ] | |
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