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EDS6432AFTA 데이터시트 PDF




Elpida Memory에서 제조한 전자 부품 EDS6432AFTA은 전자 산업 및 응용 분야에서
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부품번호 EDS6432AFTA 기능
기능 64M bits SDRAM
제조업체 Elpida Memory
로고 Elpida Memory 로고


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EDS6432AFTA 데이터시트, 핀배열, 회로
DATA SHEET
64M bits SDRAM
EDS6432AFTA, EDS6432CFTA
(2M words × 32 bits)
Description
The EDS6432AFTA, EDS6432CFTA are 64M bits
SDRAMs organized as 524,288 words × 32 bits × 4
banks. All inputs and outputs are synchronized with
www.DataSheet4Ut.hcoempositive edge of the clock.
Supply voltages are 3.3V (EDS6432AFTA) and 2.5V
(EDS6432CFTA).
It is packaged in 86-pin plastic TSOP (II).
Features
3.3V and 2.5V power supply
Clock frequency: 166MHz/133MHz (max.)
Single pulsed /RAS
• ×32 organization
4 banks can operate simultaneously and
independently
Burst read/write operation and burst read/single
write operation capability
2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8, full page)
Interleave (BL = 1, 2, 4, 8)
Programmable /CAS latency (CL): 2, 3
Byte control by DQM
Refresh cycles: 4096 refresh cycles/64ms
2 variations of refresh
Auto refresh
Self refresh
TSOP (II) package with lead free solder (Sn-Bi)
RoHS compliant
Pin Configurations
/xxx indicate active low signal.
86-pin Plastic TSOP(II)
VDD 1
DQ0 2
VDDQ 3
DQ1 4
DQ2 5
VSSQ 6
DQ3 7
DQ4 8
VDDQ 9
DQ5 10
DQ6 11
VSSQ 12
DQ7 13
NC 14
VDD 15
DQM0 16
/WE 17
/CAS 18
/RAS 19
/CS 20
NC 21
BA0 22
BA1 23
A10(AP) 24
A0 25
A1 26
A2 27
DQM2 28
VDD 29
NC 30
DQ16 31
VSSQ 32
DQ17 33
DQ18 34
VDDQ 35
DQ19 36
DQ20 37
VSSQ 38
DQ21 39
DQ22 40
VDDQ 41
DQ23 42
VDD 43
86 VSS
85 DQ15
84 VSSQ
83 DQ14
82 DQ13
81 VDDQ
80 DQ12
79 DQ11
78 VSSQ
77 DQ10
76 DQ9
75 VDDQ
74 DQ8
73 NC
72 VSS
71 DQM1
70 NC
69 NC
68 CLK
67 CKE
66 A9
65 A8
64 A7
63 A6
62 A5
61 A4
60 A3
59 DQM3
58 VSS
57 NC
56 DQ31
55 VDDQ
54 DQ30
53 DQ29
52 VSSQ
51 DQ28
50 DQ27
49 VDDQ
48 DQ26
47 DQ25
46 VSSQ
45 DQ24
44 VSS
(Top view)
A0 to A10 Address input
BA0, BA1 Bank select address
DQ0 to DQ31 Data-input/output
/CS Chip select
/RAS
Row address strobe
/CAS
Column address strobe
/WE Write enable
DQM0 to DQM3 Input output mask
CKE
Clock enable
CLK Clock input
VDD
Power for internal circuit
VSS
Ground for internal circuit
VDDQ
Power for DQ circuit
VSSQ
Ground for DQ circuit
NC No connection
Document No. E0487E50 (Ver. 5.0)
Date Published June 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004-2005




EDS6432AFTA pdf, 반도체, 판매, 대치품
EDS6432AFTA, EDS6432CFTA
Electrical Specifications
All voltages are referenced to VSS (GND).
After power up, execute power up sequence and initialization sequence before proper device operation is achieved
(refer to the Power up sequence).
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS
[EDS6432AF]
[EDS6432CF]
Symbol
VT
VT
Rating
–0.5 to VDD + 0.5 (4.6 (max.))
–0.5 to VDD + 0.5 (3.6 (max.))
Unit
V
V
Note
Supply voltage relative to VSS
[EDS6432AF]
[EDS6432CF]
VDD
VDD
–0.5 to +4.6
–0.5 to +3.6
V
V
Short circuit output current
www.DataSheet4U.Pcoowmer dissipation
IOS 50
PD 1.0
mA
W
Operating ambient temperature
TA
0 to +70
°C
Storage temperature
Tstg –55 to +125
°C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0°C to +70°C)
[EDS6432AF]
Parameter
Symbol
min.
max.
Supply voltage
VDD, VDDQ
3.0
3.6
VSS, VSSQ
0
0
Input high voltage
VIH 2.0
VDD + 0.3
Input low voltage
VIL –0.3
0.8
Notes: 1. The supply voltage with all VDD and VDDQ pins must be on the same level.
2. The supply voltage with all VSS and VSSQ pins must be on the same level.
3. VIH (max.) = VDD + 1.5V (pulse width 5ns).
4. VIL (min.) = VSS – 1.5V (pulse width 5ns).
Unit
V
V
V
V
Notes
1
2
3
4
[EDS6432CF]
Parameter
Symbol
min.
max.
Supply voltage
VDD, VDDQ
2.3
2.7
VSS, VSSQ
0
0
Input high voltage
VIH 1.7
VDD + 0.3
Input low voltage
VIL –0.3
0.7
Notes: 1. The supply voltage with all VDD and VDDQ pins must be on the same level.
2. The supply voltage with all VSS and VSSQ pins must be on the same level.
3. VIH (max.) = VDD + 1.5V (pulse width 5ns).
4. VIL (min.) = VSS – 1.5V (pulse width 5ns).
Unit
V
V
V
V
Notes
1
2
3
4
Data Sheet E0487E50 (Ver. 5.0)
4

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EDS6432AFTA 전자부품, 판매, 대치품
EDS6432AFTA, EDS6432CFTA
AC Characteristics (TA = 0°C to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V) [EDS6432AF]
(TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [EDS6432CF]
-6B -75
Parameter
Symbol min.
max.
min.
max.
Unit Notes
System clock cycle time
(CL = 2)
(CL = 3)
tCK 10 — 10 — ns 1
tCK 6
— 7.5 — ns 1
CLK high pulse width
tCH 2.5
2.5 —
ns 1
CLK low pulse width
tCL 2.5 —
2.5 —
ns 1
Access time from CLK
tAC —
5.4 —
5.4 ns 1, 2
Data-out hold time
tOH 2
—2
— ns 1, 2
CLK to Data-out low impedance
tLZ 0
—0
— ns 1, 2, 3
www.DataSheet4UC.cLoKmto Data-out high impedance
Input setup time
tHZ —
5.4 —
5.4 ns 1, 4
tSI 1.5 —
1.5 —
ns 1
Input hold time
tHI 0.8 —
0.8 —
ns 1
Ref/Active to Ref/Active command period tRC
60
67.5 —
ns 1
Active to Precharge command period
Active command to column command
(same bank)
Precharge to active command period
Write recovery or data-in to precharge lead
time
Last data into active latency
tRAS
tRCD
tRP
tDPL
tDAL
Active (a) to Active (b) command period
tRRD
42
18
18
12
2CLK +
18ns
12
120000
45
20
20
15
2CLK +
20ns
15
120000
ns
ns
ns
ns
ns
1
1
1
1
1
Transition time (rise and fall)
tT 0.5 5
0.5 5
ns
Refresh period
(4096 refresh cycles)
tREF
64
64
ms
Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V(EDS6432AF)
and 1.2V (EDS6432CF).
2. Access time is measured at 1.4V(EDS6432AF) and 1.2V (EDS6432CF). Load condition is CL = 30pF.
3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
Data Sheet E0487E50 (Ver. 5.0)
7

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