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EDS6432AFBH 데이터시트 PDF




Elpida Memory에서 제조한 전자 부품 EDS6432AFBH은 전자 산업 및 응용 분야에서
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부품번호 EDS6432AFBH 기능
기능 64M bits SDRAM
제조업체 Elpida Memory
로고 Elpida Memory 로고


EDS6432AFBH 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



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EDS6432AFBH 데이터시트, 핀배열, 회로
DATA SHEET
64M bits SDRAM
EDS6432AFBH, EDS6432CFBH
(2M words × 32 bits)
Description
The EDS6432AFBH, EDS6432CFBH are 64M bits
SDRAMs organized as 524,288 words × 32 bits × 4
banks. All inputs and outputs are synchronized with
www.DataSheet4Ut.hcoempositive edge of the clock.
Supply voltages are 3.3V (EDS6432AFBH) and 2.5V
(EDS6432CFBH).
They are packaged in 90-ball FBGA.
Features
3.3V and 2.5V power supply
Clock frequency: 166MHz/133MHz (max.)
Single pulsed /RAS
• ×32 organization
4 banks can operate simultaneously and
independently
Burst read/write operation and burst read/single
write operation capability
Programmable burst length (BL): 1, 2, 4, 8, full page
2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8, full page)
Interleave (BL = 1, 2, 4, 8)
Programmable /CAS latency (CL): 2, 3
Byte control by DQM
Refresh cycles: 4096 refresh cycles/64ms
2 variations of refresh
Auto refresh
Self refresh
FBGA package with lead free solder (Sn-Ag-Cu)
RoHS compliant
Pin Configurations
/xxx indicate active low signal.
90-ball FBGA
123456789
A
DQ26 DQ24 VSS
B
DQ28 VDDQ VSSQ
C
VSSQ DQ27 DQ25
D
VSSQ DQ29 DQ30
E
VDDQ DQ31 NC
F
VSS DQM3 A3
G
A4 A5 A6
H
A7 A8 NC
J
CLK CKE A9
K
DQM1 NC NC
L
VDDQ DQ8 VSS
M
VSSQ DQ10 DQ9
N
VSSQ DQ12 DQ14
P
DQ11 VDDQ VSSQ
R
DQ13 DQ15 VSS
(Top view)
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC DQ16 VSSQ
A2 DQM2 VDD
A10 A0 A1
NC BA1 NC
BA0 /CS /RAS
/CAS /WE DQM0
VDD DQ7 VSSQ
DQ6 DQ5 VDDQ
DQ1 DQ3 VDDQ
VDDQ VSSQ DQ4
VDD DQ0 DQ2
A0 to A10
BA0, BA1
DQ0 to DQ31
/CS
/RAS
/CAS
/WE
DQM0 to DQM3
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Address inputs
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
DQ mask enable
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0497E20 (Ver. 2.0)
Date Published July 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004-2005




EDS6432AFBH pdf, 반도체, 판매, 대치품
EDS6432AFBH, EDS6432CFBH
Electrical Specifications
All voltages are referenced to VSS (GND).
After power up, execute power up sequence and initialization sequence before proper device operation is achieved
(refer to the Power up sequence).
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS
[EDS6432AF]
[EDS6432CF]
Symbol
VT
VT
Rating
–0.5 to VDD + 0.5 (4.6 (max.))
–0.5 to VDD + 0.5 (3.6 (max.))
Unit
V
V
Note
Supply voltage relative to VSS
[EDS6432AF]
[EDS6432CF]
VDD
VDD
–0.5 to +4.6
–0.5 to +3.6
V
V
Short circuit output current
www.DataSheet4U.Pcoowmer dissipation
IOS 50
PD 1.0
mA
W
Operating ambient temperature
TA
0 to +70
°C
Storage temperature
Tstg –55 to +125
°C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0°C to +70°C)
[EDS6432AF]
Parameter
Symbol
min.
max.
Supply voltage
VDD, VDDQ
3.0
3.6
VSS, VSSQ
0
0
Input high voltage
VIH 2.0
VDD + 0.3
Input low voltage
VIL –0.3
0.8
Notes: 1. The supply voltage with all VDD and VDDQ pins must be on the same level.
2. The supply voltage with all VSS and VSSQ pins must be on the same level.
3. VIH (max.) = VDD + 1.5V (pulse width 5ns).
4. VIL (min.) = VSS – 1.5V (pulse width 5ns).
Unit
V
V
V
V
Notes
1
2
3
4
[EDS6432CF]
Parameter
Symbol
min.
max.
Supply voltage
VDD, VDDQ
2.3
2.7
VSS, VSSQ
0
0
Input high voltage
VIH 1.7
VDD + 0.3
Input low voltage
VIL –0.3
0.7
Notes: 1. The supply voltage with all VDD and VDDQ pins must be on the same level.
2. The supply voltage with all VSS and VSSQ pins must be on the same level.
3. VIH (max.) = VDD + 1.5V (pulse width 5ns).
4. VIL (min.) = VSS – 1.5V (pulse width 5ns).
Unit
V
V
V
V
Notes
1
2
3
4
Data Sheet E0497E20 (Ver. 2.0)
4

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EDS6432AFBH 전자부품, 판매, 대치품
EDS6432AFBH, EDS6432CFBH
AC Characteristics (TA = 0°C to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V) [EDS6432AF]
(TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [EDS6432CF]
-6B -75
Parameter
Symbol min.
max.
min.
max.
Unit Notes
System clock cycle time
(CL = 2)
(CL = 3)
tCK 10 — 10 — ns 1
tCK 6
— 7.5 — ns 1
CLK high pulse width
tCH 2.5
2.5 —
ns 1
CLK low pulse width
tCL 2.5 —
2.5 —
ns 1
Access time from CLK
tAC —
5.4 —
5.4 ns 1, 2
Data-out hold time
tOH 2
—2
— ns 1, 2
CLK to Data-out low impedance
tLZ 0
—0
— ns 1, 2, 3
www.DataSheet4UC.cLoKmto Data-out high impedance
Input setup time
tHZ —
5.4 —
5.4 ns 1, 4
tSI 1.5 —
1.5 —
ns 1
Input hold time
tHI 0.8 —
0.8 —
ns 1
Ref/Active to Ref/Active command period tRC
60
67.5 —
ns 1
Active to Precharge command period
Active command to column command
(same bank)
Precharge to active command period
Write recovery or data-in to precharge lead
time
Last data into active latency
tRAS
tRCD
tRP
tDPL
tDAL
Active (a) to Active (b) command period
tRRD
42
18
18
12
2CLK +
18ns
12
120000
45
20
20
15
2CLK +
20ns
15
120000
ns
ns
ns
ns
ns
1
1
1
1
1
Transition time (rise and fall)
tT 0.5 5
0.5 5
ns
Refresh period
(4096 refresh cycles)
tREF
64
64
ms
Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V(EDS6432AF)
and 1.2V (EDS6432CF).
2. Access time is measured at 1.4V(EDS6432AF) and 1.2V (EDS6432CF). Load condition is CL = 30pF.
3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
Data Sheet E0497E20 (Ver. 2.0)
7

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