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부품번호 | EDS6416AHBH 기능 |
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기능 | 64M bits SDRAM | ||
제조업체 | Elpida Memory | ||
로고 | |||
DATA SHEET
64M bits SDRAM
EDS6416AHBH, EDS6416CHBH
(4M words × 16 bits)
Description
The EDS6416AHBH, EDS6416CHBH are 64M bits
SDRAMs organized as 1,048,576 words × 16 bits × 4
banks. All inputs and outputs are synchronized with
www.DataSheet4Ut.hcoempositive edge of the clock.
Supply voltages are 3.3V (EDS6416AHBH) and 2.5V
(EDS6416CHBH).
It is packaged in 60-ball FBGA.
Features
• 3.3V and 2.5V power supply
• Clock frequency: 166MHz/133MHz (max.)
• Single pulsed /RAS
• ×16 organization
• 4 banks can operate simultaneously and
independently
• Burst read/write operation and burst read/single
write operation capability
• 2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8, full page)
Interleave (BL = 1, 2, 4, 8)
• Programmable /CAS latency (CL): 2, 3
• Byte control by UDQM and LDQM
• Refresh cycles: 4096 refresh cycles/64ms
• 2 variations of refresh
Auto refresh
Self refresh
• FBGA package with lead free solder (Sn-Ag-Cu)
RoHS compliant
Pin Configurations
/xxx indicate active low signal.
60-ball FBGA
1234567
A
VSS DQ15
B
DQ14 VSSQ
C
DQ13 VDDQ
D
DQ12 DQ11
DQ0 VDD
VDDQ DQ1
VSSQ DQ2
DQ4 DQ3
E
DQ10 VSSQ
VDDQ DQ5
F
DQ9 VDDQ
G
DQ8 NC
VSSQ DQ6
NC DQ7
H
NC VSS
J
NC UDQM
VDD NC
LDQM /WE
K
NC CLK
L
CKE NC
M
A11 A9
N
A8 A7
P
A6 A5
R
VSS A4
/RAS /CAS
NC /CS
BA1 BA0
A0 A10
A2 A1
A3 VDD
(Top view)
A0 to A11
BA0, BA1
DQ0 to DQ15
/CS
/RAS
/CAS
/WE
LDQM, UDQM
Address input
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
Input/output mask
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0442E40 (Ver. 4.0)
Date Published June 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004-2005
EDS6416AHBH, EDS6416CHBH
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, execute power up sequence and initialization sequence before proper device operation is achieved
(refer to the Power up sequence).
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS
[EDS6416AH]
[EDS6416CH]
Symbol
VT
VT
Rating
–0.5 to VDD + 0.5 (≤ 4.6 (max.))
–0.5 to VDD + 0.5 (≤ 3.6 (max.))
Unit
V
V
Note
Supply voltage relative to VSS
[EDS6416AH]
[EDS6416CH]
VDD
VDD
–0.5 to +4.6
–0.5 to +3.6
V
V
Short circuit output current
www.DataSheet4U.Pcoowmer dissipation
IOS 50
PD 1.0
mA
W
Operating ambient temperature
TA
0 to +70
°C
Storage temperature
Tstg –55 to +125
°C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0°C to +70°C)
[EDS6416AH]
Parameter
Symbol
min.
max.
Supply voltage
VDD, VDDQ
3.0
3.6
VSS, VSSQ
0
0
Input high voltage
VIH 2.0
VDD + 0.3
Input low voltage
VIL –0.3
0.8
Notes: 1. The supply voltage with all VDD and VDDQ pins must be on the same level.
2. The supply voltage with all VSS and VSSQ pins must be on the same level.
3. VIH (max.) = VDD + 1.5V (pulse width ≤ 5ns).
4. VIL (min.) = VSS – 1.5V (pulse width ≤ 5ns).
Unit
V
V
V
V
Notes
1
2
3
4
[EDS6416CH]
Parameter
Symbol
min.
max.
Supply voltage
VDD, VDDQ
2.3
2.7
VSS, VSSQ
0
0
Input high voltage
VIH 1.7
VDD + 0.3
Input low voltage
VIL –0.3
0.7
Notes: 1. The supply voltage with all VDD and VDDQ pins must be on the same level.
2. The supply voltage with all VSS and VSSQ pins must be on the same level.
3. VIH (max.) = VDD + 1.5V (pulse width ≤ 5ns).
4. VIL (min.) = VSS – 1.5V (pulse width ≤ 5ns).
Unit
V
V
V
V
Notes
1
2
3
4
Data Sheet E0442E40 (Ver. 4.0)
4
4페이지 EDS6416AHBH, EDS6416CHBH
AC Characteristics (TA = 0°C to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V) [EDS6416AH]
(TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [EDS6416CH]
-6B -75
Parameter
Symbol min.
max.
min.
max.
Unit Notes
System clock cycle time
(CL = 2)
(CL = 3)
tCK 10 — 10 — ns 1
tCK 6
— 7.5 — ns 1
CLK high pulse width
tCH 2.5
—
2.5 —
ns 1
CLK low pulse width
tCL 2.5 —
2.5 —
ns 1
Access time from CLK
tAC —
5.4 —
5.4 ns 1, 2
Data-out hold time
tOH 2
—2
— ns 1, 2
CLK to Data-out low impedance
tLZ 0
—0
— ns 1, 2, 3
www.DataSheet4UC.cLoKmto Data-out high impedance
Input setup time
tHZ —
5.4 —
5.4 ns 1, 4
tSI 1.5 —
1.5 —
ns 1
Input hold time
tHI 0.8 —
0.8 —
ns 1
Ref/Active to Ref/Active command period tRC
60
—
67.5 —
ns 1
Active to Precharge command period
Active command to column command
(same bank)
Precharge to active command period
Write recovery or data-in to precharge lead
time
Last data into active latency
tRAS
tRCD
tRP
tDPL
tDAL
Active (a) to Active (b) command period
tRRD
42
18
18
12
2CLK +
18ns
12
120000
—
—
—
—
—
45
20
20
15
2CLK +
20ns
15
120000
—
—
—
—
—
ns
ns
ns
ns
ns
1
1
1
1
1
Transition time (rise and fall)
tT 0.5 5
0.5 5
ns
Refresh period
(4096 refresh cycles)
tREF
—
64
—
64
ms
Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V(EDS6416AH)
and 1.2V (EDS6416CH).
2. Access time is measured at 1.4V(EDS6416AH) and 1.2V (EDS6416CH). Load condition is CL = 30pF.
3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
Data Sheet E0442E40 (Ver. 4.0)
7
7페이지 | |||
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부품번호 | 상세설명 및 기능 | 제조사 |
EDS6416AHBH | 64M bits SDRAM | Elpida Memory |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |