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PDF LIS1R02 Data sheet ( Hoja de datos )
| Número de pieza | LIS1R02 | |
| Descripción | ANGULAR ACCELEROMETER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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LIS1R02 (L6671)
s HIGH SENSITIVITY 2.5 rad/sec2
s 8 BIT A/D CONVERTER
s 800 Hz BANDWIDTH
s 200 rad/sec2 FULL SCALE VALUE
s DIGITAL DOWNSAMPLING
s DIGITAL FILTERING
s 3.3V 3WIRES SERIAL INTERFACE
(5V TOLLERANCE)
s EMBEDDED PLL
ANGULAR ACCELEROMETER
PRODUCT PREVIEW
SO24
ORDERING NUMBER: LIS1R02
DESCRIPTION
The LIS1R02 is a complete rotational accelerometer
system based on a Σ∆ architecture, followed by a
digital downsampling block and a digital filter, featur-
ing high sensitivity, 800 Hz signal bandwidth and a
complete serial port interface for a direct connection
BLOCK DIAGRAM
to microprocessor environment. An embedded PLL
allows internal clock generation from an external syn-
chronization signal.
SENSOR
A/D
CONVERTER
DIGITAL
FILTER
Clk-IN
PLL
SER.
IFC
SPE
SPD
SPC
D02IN1363
April 2002
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/11
1 page  
LIS1R02 (L6671)
SERIAL PORT, REGISTERS, EPROM and TEST MODES
1.0 SERIAL PORT
1.1 READ & WRITE REGISTERS
Figure 2.
SPE
SPC
SPD
RW ID2 ID1 ID0 AD3 AD2 AD1 AD0 D7 D6 D5 D4 D3 D2 D1 D0
D00IN1119
SPE is the Serial Port Enable. It goes high at the start of the transmission and goes back low at the end. SPC
is the Serial Port Clock. It is stopped high when SPE is low (no transmission). SPD is the Serial Port Data. It is
driven by the falling edge of SPC. It should be captured at the rising edge of SPC.
The Read Register or Write Register command consists of 16 clocks or bit. A bit duration is the time between
two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the rising edge of SPE
and the last bit (bit 15) starts at the last falling edge of SPC just before the falling edge of SPE.
s bit 0 : RW bit. When 0, the data (D7:0) is written into the device. When 1, the data (D7:0) from the device
is read. In this case, the LIS1R02 will drive SPD at the start of bit 8.
s bit 1-3 : chip ID. The chip ID for the LIS1R02 is ID(2:0)=110. The device accepts the command only
when the ID is valid (equal to 110).
s bit 4-7 : address AD(3:0). This is the address field for the registers. See section 2 for more details.
s bit 8-15 : data D(7:0). This is the data that will be written (read) into (from) the register whose address
is AD(3:0).
1.2 READ FIFO
Figure 3.
SPE
SPC
SPD
RW ID2 ID1 ID0 AD3 AD2 AD1 AD0 D7-0 D6-0 ..... D0-0 D7-1 D6-1 ..... D0-1
D00IN1120
The Read FIFO command consists of 24 clocks or bits.
bit 0 : READ bit. The value is 1.
bit 1-3 : chip ID. ID(2:0)=110.
bit 4-7 : FIFO address.
bit 8-23: FIFO data.
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5 Page 
LIS1R02 (L6671)
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
® 2002 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco -
Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.
http://www.st.com
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