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PDF ZL63039 Data sheet ( Hoja de datos )
| Número de pieza | ZL63039 | |
| Descripción | 12x6.25 Gb/s Multirate VCSEL Driver | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ZL63039 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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ZL63039
12x6.25 Gb/s Multirate VCSEL Driver
Data Sheet
January 2008
Features
• Single +3.3 V supply dissipating 70 mW
per channel
• 12-channel VCSEL driver operates from
DC to 6.25Gb/s
• Individual channel control for enable, drive
currents, and VCSEL fault control
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• Adjustable temperature compensation
for threshold and modulation drive currents
• Selectable analog multiplexer provides
junction temperature, supply voltage, and
VCSEL bias current for each channel
• Programmable VCSEL fault detection with
autonomous fault handling and interrupt
• Squelch automatically disables channel
when input amplitude falls below
programmable threshold
• Adjustable VCSEL peaking control
• 2-wire interface provides access to internal
registers
• IC dimensions 2245 x 3870 um
• 250-micron channel pitch matches optical
ribbon fiber and VCSEL arrays
• Differential CML compatible inputs
with on-chip termination
Applications
• Single data rate (SDR) and double data
rate (DDR) XAUI
• Single data rate (SDR) and double data
rate (DDR) Infiniband®
• 1x, 2x, 4x Fiber Channel
• Gigabit Ethernet
• PCI Express 1.0 and 2.0
• SNAP12 optical modules
• Proprietary and CWDM parallel optical
modules
Description
The growing use of the Internet has created
increasingly higher demand for multi-Gb/s I/O
performance. The demand for 40 Gb/s
bandwidth and beyond fuels the growth of short-
reach 10 Gb/s infrastructures within high-end
telco and datacom routers, switches, servers and
other proprietary chassis-to-chassis links.
The Zarlink ZL63039 12x6.25Gb/s VCSEL Driver
is a 12-channel VCSEL driver designed
for various parallel optics and CWDM PMD
applications. It consists of a DC-coupled
amplifier with selectable threshold and
modulation currents optimized for driving
commercially available, common cathode
VCSELs from a single +3.3 V supply.
Individual channel settings are used to control the
threshold and modulation drive current and their
temperature coefficients, allowing the optical
output power and extinction ratio to be optimized.
A selectable analog multiplexer provides junction
temperature, supply voltage, and VCSEL bias
current for each channel to enable optical module
diagnostic features.
Data controlling the Zarlink ZL63039 VCSEL
driver settings is loaded by a simple 2-wire serial
serial interface reducing the number of pins
required of a microcontroller.
Page 1
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2008, Zarlink Semiconductor Inc. All Rights Reserved.
1 page  
ZL63039
Data Sheet
Temperature Compensation
The temperature compensation circuits for Imax and Imin each have four operating modes as shown in
Table 2. The circuits independently compensate the drive currents depending on the IC temperature
above 25 ºC and the TC_MAX[1:0] and TC_MIN[1:0] setting as seen in Figures 5 and 6.
TC_MAX[1:0], TC_MIN[1:0] Input
Imax Current Increase
Imin Current Increase
00 0 0
01
0.18
0.2
10
0.36
0.4
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11
0.54
0.6
Table 2: Temperature Compensation Settings
Unit
% / °C
% / °C
% / °C
% / °C
50
TC_MAX[1:0]=[11]
40
30 [10]
20
[01]
10
[00]
0
0 25 50 75 100
Temperature (°C)
Figure 5: Drive current (Imax) temperature
compensation vs temperature for each setting
50
TC_MIN[1:0]=[11]
40
30 [10]
20
[01]
10
[00]
0
0 25 50 75 100
Temperature (°C)
Figure 6: Drive current (Imin) temperature
compensation vs temperature for each setting
Enable
The high-speed channels of the ZL63039 are controlled globally with the TX_EN and TX_DIS input. The
ENMODE[1:0] register bits allow the user to connect or disconnect pull-up and pull-down resistors on
the TX_EN and TX_DIS inputs. The four modes of ENMODE are shown in Table 3. Note that
ENMODE[1:0]=00 is the default setting.
Individual channels may be enabled or disabled with the 2-wire interface through the CHANNEL register.
ENMODE[1:0]
TX_EN
TX_DIS
00 (POR)
Pull-down
Pull-up
01
Open
Pull-down
10
Open
Open
11
Pull-up
Pull-down
Table 3: TX_EN and TX_DIS Resistor Configurations using ENMODE[1:0]
Page 5
Zarlink Semiconductor Inc.
5 Page 
ZL63039
Data Sheet
Critical Timing
The register read, register write, and clear interrupt 2-wire transactions share the same timing requirements.
Figures 11 and 12 show critical timing relationships and Table 12 provides worst case timing.
start
stop
DATA
A
A
A
A
R
R
WR
RD
D
D
D
D
D
D
D
D
D…
DD
3210210
1 2 3 4 5 6 7 8 9 10
n-1 n
CLOCK
…
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t1
t2
start
t3
t4 t5
t6
t7 t8 t9
Figure 11: Register Write Sequence with Timing Relationships
byte_1
byte_n
stop
DATA
AAAARRR
DDDDDDDD
D … D D NACK
3210210
0 1 2 3 4 5 6 7 ACK 0
WR
67
CLOCK
…
t10 t11
t10
Figure 12: Register Read Sequence with Timing Relationships
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
Description
Worst Case Timing (ns)
Start condition to first clock transition
0.2
Write data to clock set time
1.2
Write data to clock hold time
0.5
Clock high
17.0
Clock low
7.0
Clock period
34.0
Last clock to last write data transition
6.0
Data=low before stop condition
0.1
Between control sequences
22.0
Read data available to clock edge
2.6
Read data delay from clock
2.1
Last clock to stop in read sequence
0.5
Table 12: Worst Case Timing for 2-wire Transactions
t12
Page 11
Zarlink Semiconductor Inc.
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ZL63039.PDF ] | |
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