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PDF MX25L6402 Data sheet ( Hoja de datos )
| Número de pieza | MX25L6402 | |
| Descripción | 64M-BIT [x 1] CMOS SERIAL eLite FlashTM MEMORY | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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MX25L6402
FEATURES
Macronix NBitTM Memory Family
64M-BIT [x 1] CMOS SERIAL eLite FlashTM MEMORY
GENERAL
• 67,108,864 x 1 bit structure
• 128 Equal Sectors with 64K byte each
- Any sector can be erased
• Single Power Supply Operation
www.DataSheet4U-.3co.0mto 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
• Low Vcc write inhibit is equal to or less than 2.2V
PERFORMANCE
• High Performance
- Fast access time: 25MHz serial clock (50pF + 1TTL
Load)
- Fast program time: 4ms/page (typical, 128-byte per
page)
- Fast erase time: 3s/sector (typical, 64K-byte per
sector)
- Acceleration mode:
- Program time: 3.2ms/page (typical)
- Erase time: 2.4s/sector (typical)
• Low Power Consumption
- Low active read current: 24mA (typical) at 25MHz
- Low active programming current: 35mA (typical)
- Low active erase current: 35mA (typical)
- Low standby current: 5uA (typical, CMOS)
• Minimum 100 erase/program cycle
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code, 3-byte address, 1-byte byte
address
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected
sector
- Automatically programs and verifies data at selected
page by an internal algroithm that automatically times
the program pulse widths (Any page to be programed
should have page in the erased state first)
• Status Register Feature
- Provides detection of program and erase operation
completion.
- Provides auto erase/ program error report
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI Input
- Serial Data Input
• SO Output
- Serial Data Output
• ACC Pin
- Program/erase acceleration
• PACKAGE
- 32-pin SOP (450mil)
P/N: PM0943
REV. 1.0, SEP. 29, 2004
1
1 page  
MX25L6402
DEVICE OPERATION
1.Before a command is issued, status register should be checked to ensure device is ready for the intended operation.
2.When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until
next CS falling edge. In standby mode, SO pin of this LSI should be High-Z.
3.When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CS
rising edge.
COMMAND DESCRIPTION
www.DataSheet(41U).cRomead Array
This command is sent with the 4-byte address (command included), and the byte address, followed by four dummy bytes
sent to give the device time to stabilize. The device will then send out data starting at the byte address until CS goes
high. The clock to clock out the data is supplied by the master SPI. The read operation is executed on whole array. If
the end of the array is reached then the device will wrap around to the beginning of the array.
(2) Read Status Register
When this command is sent, the device will continuously send out the status register contents starting at bit7. The clock
to clock out the data is supplied by the master SPI.
bit7
bit6 bit5 bit4 bit3
bit2 bit1
program/erase
NA
NA
erase
program NA
NA
completion
error error
Note1
1=error 1=error
bit0
ready/busy
1=ready
0=busy
Bit 6,5,2,1 = Reserve for future use.
Bit 4 = "1" -----> There is an error occurred in last erase operation.
= "0" -----> There is no error occurred in last erase operation.
Bit 3 = "1" -----> There is an error occurred in last program operation.
= "0" -----> There is no error occurred in last program operation.
Bit 0 ="1" -----> Device is in ready mode.
="0" -----> Device is in busy mode.
Note 1: The initial value of Bit7 is "1". Bit7 will have "1" to "0" transit only after program/erase operation is completed. Bit7
will shift from "0" to "1" only after issued program/erase/Clear status register command. Please note the Bit7=0 if program/
erase fail.
Note 2: The value of Bit 0 is "1", no matter the result of program/erase is pass or fail.
(3) Clear Status Register
This command only resets erase error bit (bit 4) and program error bit (bit 3) . These two bits are set by on-chip state machine
during program/erase operation, and can only be reset by issuing a clear status register command or by powering down
VCC .
If status register indicates that error occurred in the last program/erase operation, any further program/erase operation will
be prohibited until status register is cleared.
(4) Read ID
This command is sent with an extra dummy byte( 2-byte command). The device will clock out manufacturer code (C2H)
and device code (9CH) when this command is issued. The clock to clock out the data is supplied by the master SPI.
P/N: PM0943
REV. 1.0, SEP. 29, 2004
5
5 Page 
MX25L6402
INPUT TEST WAVEFORMS AND MEASURESMENT LEVEL
3.0V
0V
1.5V
AC
Measurement
Level
Note:Input pulse rise and fall time are < 10ns
www.DataSheet4U.com
OUTPUT LOADING
DEVICE UNDER
TEST
+3.3V
CL
DIODES=IN3064
OR EQUIVALENT
CL=50pF Including jig capacitance
P/N: PM0943
REV. 1.0, SEP. 29, 2004
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| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet MX25L6402.PDF ] | |
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