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MX25L8005 데이터시트 PDF




MXIC에서 제조한 전자 부품 MX25L8005은 전자 산업 및 응용 분야에서
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PDF 형식의 MX25L8005 자료 제공

부품번호 MX25L8005 기능
기능 (MX25L4005 / MX25L8005) 4M/8M-Bit CMOS Serial Flash
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MX25L8005 데이터시트, 핀배열, 회로
PRELIMINARY
MX25L4005, MX25L8005
FEATURES
GENERAL
• Serial Peripheral Interface (SPI) compatible -- Mode 0
and Mode 3
• 4,194,304 x 1 bit structure for 4M; 8,388,608 x 1 bit
structure for 8M
www.DataSheet4U1.2co8mEqual Sectors with 4K byte each (MX25L4005)
256 Equal Sectors with 4K byte each (MX25L8005)
- Any Sector can be erased individually
• 8 Equal Blocks with 64K byte each (MX25L4005)
16 Equal Blocks with 64K byte each (MX25L8005)
- Any Block can be erased individually
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
• Low Vcc write inhibit is from 1.5V to 2.5V
PERFORMANCE
• High Performance
- Fast access time: 70MHz serial clock (15pF + 1TTL
Load) and 66MHz serial clock (30pF + 1TTL Load)
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page
(256-byte per page)
- Fast erase time: 90ms(typ.) and 270ms(max.)/sector
(4K-byte per sector) ; 1s(typ.) and 3s(max.)/block (64K-
byte per block)
• Low Power Consumption
- Low active read current: 12mA(max.) at 70MHz,
8mA(max.) at 66MHz and 4mA(max.) at 33MHz
- Low active programming current: 30mA (max.)
- Low active erase current: 15mA (max.)
- Low standby current: 50uA (max.)
- Deep power-down mode 1uA (typical)
• Minimum 100,000 erase/program cycles
4M/8M-BIT [x 1] CMOS SERIAL FLASH
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Block Lock protection
- The BP0~BP2 status bit defines the size of the area
to be software protected against Program and Erase
instructions.
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected
sector
- Automatically programs and verifies data at selected
page by an internal algorithm that automatically times
the program pulse widths (Any page to be programed
should have page in the erased state first)
Status Register Feature
Electronic Identification
- JEDEC 2-byte Device ID
- RES command, 1-byte Device ID
HARDWARE FEATURES
SCLK Input
- Serial clock input
• SI Input
- Serial Data Input
• SO Output
- Serial Data Output
• WP# pin
- Hardware write protection
• HOLD# pin
- pause the chip without diselecting the chip
• PACKAGE
- 8-pin SOP (150mil)
- 8-pin SOP (200mil)
- 8-land SON (6x5mm)
P/N: PM1130
REV. 0.04, MAY. 31, 2005
1




MX25L8005 pdf, 반도체, 판매, 대치품
MX25L4005, MX25L8005
DATA PROTECTION
The MX25L4005, MX25L8005 are designed to offer
protection against accidental erasure or programming
caused by spurious system level signals that may exist
during power transition. During power up the device
automatically resets the state machine in the Read mode.
In addition, with its control register architecture, alteration
of the memory contents only occurs after successful
completion of specific command sequences. The device
also incorporates several features to prevent inadvertent
www.DataSheetw4Uri.tceocmycles resulting from VCC power-up and power-down
transition or system noise.
Power-On Reset and an internal timer (tPUW) can
provide protection against inadvertant changes while
the power supply is outside the operating specification.
Program, Erase and Write Status Register instructions
are checked that they consist of a number of clock
pulses that is a multiple of eight, before they are
accepted for execution.
All instructions that modify data must be preceded by
a Write Enable (WREN) instruction to set the Write
Enable Latch (WEL) bit . This bit is returned to its reset
state by the following events:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion
The Block Protect (BP2, BP1, BP0) bits allow part of
the memory to be configured as readonly. This is the
Software Protected Mode (SPM).
The Write Protect (WP#) signal allows the Block
Protect (BP2, BP1, BP0) bits and Status Register
Write Disable (SRWD) bit to be protected. This is the
Hardware Protected Mode (HPM).
In addition to the low power consumption feature, the
Deep Power-down mode offers extra software protec-
tion from inadvertent Write, Program and Erase in-
structions, as all instructions are ignored except one
particular instruction (the Release from Deep
Powerdown instruction).
To avoid unexpected changes by system power supply
transition, the Power-On Reset and an internal timer
(tPUW) can protect the device.
Before the Program, Erase, and Write Status Register
execution, instruction length will be checked on follow-
ing the clock pulse number to be multiple of eight base.
Write Enable (WREN) instruction must set to Write
Enable Latch (WEL) bit before writing other instructions
to modify data. The WEL bit will return to reset state by
following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion
The Software Protected Mode (SPM) use (BP2, BP1,
BP0) bits to allow part of memory to be protected as
read only.
The Hardware Protected Mode (HPM) use WP# to
protect the (BP2, BP1, BP0) bits and SRWD bit.
Deep-Power Down Mode also protects the device by
ignoring all instructions except Release from Deep-
Power Down (RDP) instruction and RES instruction.
P/N: PM1130
REV. 0.04, MAY. 31, 2005
4

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MX25L8005 전자부품, 판매, 대치품
MX25L4005, MX25L8005
Table 2. COMMAND DEFINITION
COMMAND WREN
(byte)
(write
Enable)
1st 06 Hex
2nd
3rd
4th
www.DataSheet4U5.tchom
Action
sets the
(WEL)
write
enable
latch bit
WRDI
(write
disable)
04 Hex
RDID
(read ident-
ification)
9F Hex
RDSR
(read status
register)
05 Hex
reset the
(WEL)
write
enable
latch bit
output the to read out
manufacturer the status
ID and 2-byte register
device ID
WRSR
(write status
register)
01 Hex
READ
(read data)
03 Hex
AD1
AD2
AD3
to write new n bytes
values to the read out
status register until
CS# goes
high
Fast Read
(fast read
data)
0B Hex
AD1
AD2
AD3
x
COMMAND SE
(byte)
(Sector
Erase)
1st 20 Hex
2nd
3rd
4th
5th
Action
AD1
AD2
AD3
BE
(Block
Erase)
52 or
D8 Hex
AD1
AD2
AD3
CE
(Chip
Erase)
60 or
C7 Hex
PP
(Page
Program)
02 Hex
DP
(Deep
Power
Down)
B9 Hex
AD1
AD2
AD3
RDP
(Release
from Deep
Power-down)
AB Hex
RES
(Read
Electronic
ID)
AB Hex
x
x
x
REMS (Read
Electronic
Manufacturer
& Device ID)
90 Hex
x
x
ADD(1)
Output the
manufacturer
ID and device
ID
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first
P/N: PM1130
REV. 0.04, MAY. 31, 2005
7

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