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90CR283 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 90CR283
기능 DS90CR283
제조업체 National Semiconductor
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90CR283 데이터시트, 핀배열, 회로
July 2001
DS90CR283/DS90CR284
28-Bit Channel Link-66 MHz
General Description
The DS90CR283 transmitter converts 28 bits of CMOS/TTL
data into four LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fifth LVDS link. Every
cycle of the transmit clock 28 bits of input data are sampled
and transmitted. The DS90CR284 receiver converts the
LVDS data streams back into 28 bits of CMOS/TTL data. At
www.DataSheet4U.caotmransmit clock frequency of 66 MHz, 28 bits of TTL data are
transmitted at a rate of 462 Mbps per LVDS data channel.
Using a 66 MHz clock, the data throughput is 1.848 Gbit/s
(231 Mbytes/s).
The multiplexing of the data lines provides a substantial
cable reduction. Long distance parallel single-ended buses
typically require a ground wire per active signal (and have
very limited noise rejection capability). Thus, for a 28-bit wide
data bus and one clock, up to 58 conductors are required.
With the Channel Link chipset as few as 11 conductors (4
data pairs, 1 clock pair and a minimum of one ground) are
needed. This provides a 80% reduction in required cable
width, which provides a system cost savings, reduces con-
nector physical size and cost, and reduces shielding require-
ments due to the cables’ smaller form factor.
The 28 CMOS/TTL inputs can support a variety of signal
combinations. For example, 7 4-bit nibbles or 3 9-bit (byte +
parity) and 1 control.
Features
n 66 MHz clock support
n Up to 231 Mbytes/s bandwidth
n Low power CMOS design (< 610 mW)
n Power Down mode (< 0.5 mW total)
n Up to 1.848 Gbit/s data throughput
n Narrow bus reduces cable size and cost
n 290 mV swing LVDS devices for low EMI
n PLL requires no external components
n Low profile 56-lead TSSOP package
n Rising edge data strobe
n Compatible with TIA/EIA-644 LVDS Standard
Block Diagrams
DS90CR283
DS90CR284
Order Number DS90CR283MTD
See NS Package Number MTD56
DS012889-27
DS012889-1
Order Number DS90CR284MTD
See NS Package Number MTD56
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2001 National Semiconductor Corporation DS012889
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90CR283 pdf, 반도체, 판매, 대치품
Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
RECEIVER SUPPLY CURRENT
ICCRW
Receiver Supply Current,
Worst Case
ICCRZ
Receiver Supply Current,
Power Down
Conditions
Min Typ Max Units
CL = 8 pF,
Worst Case Pattern
f = 32.5 MHz
f = 37.5 MHz
(Figures 1, 3)
f = 66 MHz
Power Down = Low
Receiver Outputs in Previous State
during Power Down Mode
64 77 mA
70 85 mA
110 140 mA
1 10 µA
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
www.DataSheet4U.com
Note 2: Typical values are given for VCC = 5.0V and TA = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except VOD and V OD).
Note 4: ESD Rating: HBM (1.5 k, 100 pF)
PLL VCC 1000V
All other pins 2000V
EIAJ (0, 200 pF) 150V
Note 5: VOS previously referred as VCM.
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
LLHT
LHLT
TCIT
TCCS
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TCIP
TCIH
TCIL
TSTC
THTC
TCCD
TPLLS
TPDD
Parameter
LVDS Low-to-High Transition Time (Figure 2)
LVDS High-to-Low Transition Time (Figure 2)
TxCLK IN Transition Time (Figure 4)
TxOUT Channel-to-Channel Skew (Note 6) (Figure 5)
Transmitter Output Pulse Position for Bit 0
f = 66 MHz
(Figure 16)
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
TxCLK IN Period (Figure 6)
TxCLK IN High Time (Figure 6)
TxCLK IN Low Time (Figure 6)
TxIN Setup to TxCLK IN (Figure 6)
TxIN Hold to TxCLK IN (Figure 6)
TxCLK IN to TxCLK OUT Delay @ 25˚C,
VCC = 5.0V (Figure 8)
Transmitter Phase Lock Loop Set (Figure 10)
Transmitter Power Down Delay (Figure 14)
Min
−0.30
1.70
3.60
5.90
8.30
10.40
12.70
15
0.35T
0.35T
5
2.5
3.5
Note 6: This limit based on bench characterization.
Typ
0.75
0.75
0
(1/7)Tclk
(2/7)Tclk
(3/7)Tclk
(4/7)Tclk
(5/7)Tclk
(6/7)Tclk
T
0.5T
0.5T
3.5
1.5
Max
1.5
1.5
8
350
0.30
2.50
4.50
6.75
9.00
11.10
13.40
50
0.65T
0.65T
8.5
10
100
Units
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
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90CR283 전자부품, 판매, 대치품
AC Timing Diagrams (Continued)
DS012889-11
FIGURE 8. DS90CR283 (Transmitter) Clock In to Clock Out Delay
www.DataSheet4U.com
DS012889-12
FIGURE 9. DS90CR284 (Receiver) Clock In to Clock Out Delay
DS012889-13
FIGURE 10. DS90CR283 (Transmitter) Phase Lock Loop Set Time
DS012889-14
FIGURE 11. DS90CR284 (Receiver) Phase Lock Loop Set Time
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90CR283

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