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PDF R8A66171SP Data sheet ( Hoja de datos )
| Número de pieza | R8A66171SP | |
| Descripción | A2RT | |
| Fabricantes | Renesas Technology | |
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R8A66171DD/SP
A2RT (ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER)
REJ03F0269-0100
Rev. 1.00
Feb.19.2008
DESCRIPTION
The R8A66171 is an integrated circuit for asynchronous serial data communications. It is used in combina-
tion with an 8-bit microprocessor and is produced using the silicon gate CMOS technology. R8A66171 is
the succession product of M66230.
FEATURES
● Baud rate generator
● 4-byte FIFO data buffer for transmission and reception
www.DataSheet●4UE.crormor detection : CRC-CCITT
● Wakeup function
● Majority-voting system by sampling three points of received data
● Transmission / reception data format ( number of bits )
Start bit 1
Data bit 8
Wakeup bit 1 or nil
Parity bit 1 or nil
Stop bit 1 or 2
● Transmission speed
500Kbps (max)
● Access time
ta (/RD-D) : 100ns
● High output current
IOH=-24mA IOL=24mA TxD, /RTS, P0, P1 pins
● Schmitt triggered input RxD, /CTS, /RESET pins
● Wide operating supply voltage range (Vcc=3.0~3.6V or Vcc=4.5~5.5V)
● Wide operating temperature range (Ta=-40~85OC)
APPLICATION
Data communication control that uses microprocessor
PIN CONFIGURATION (TOP VIEW)
D0
D1
DATA BUS
D2
D3
D4
D5
D6
D7
READ CONTROL INPUT RD
WRITE CONTROL INPUT WR
COMMAND/DATA C/D
CONTROL INPUT GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 TxD TRANSMISSION DATA OUTPUT
22 RxD RECEPTION DATA INPUT
21 CTS CLEAR-TO-SEND INPUT
20 RTS REQUEST-TO-SEND OUTPUT
19 P0
PORT OUTPUT
18 P1
17 INT INTERRUPT OUTPUT
16 CS CHIP SELECT INPUT
15 RESET RESET INPUT
14 X1 CLOCK INPUT
13 X2 CLOCK OUTPUT
REJ03F269-0100 Rev.1.00 Feb.19.2008
Page 1 of 22
1 page  
R8A66171DD/SP
DISCRIPTION OF FUNCTION
● Baud rate generator
The 8-bit programmable divider (baud rate generator) generates the baud rate for transmit or receive.
The division rate is (n+1) with a range of n=0~255. The baud rate is calculated by the following
formula:
baud rate
=
f(X1)
prescaler division (2 or 32) baud rate generator division rate (n+1) 16
The prescaler division rate is set by the D0 bit of command1. The baud rate generator division rate is
set by command2.
Example as follows:
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9600bps
=
9.8304MHz
2 (31+1) 16
● Block length counter
The R8A66171 can handle multiple-bytes of data as one block (packet).
Therefore, CRC of bytes is possible. The block length counter is a 6-bit programmable counter. The
block length is (m+1) bytes with the allowed values of m=0~63.
● Transmit data buffer (FIFO)
The transmit data buffer (FIFO) consists of 4-bytes.
The transmit data buffer (FIFO) functions according to the block length.
Block length=1~3
When the transmit data buffer (FIFO) becomes empty (buffer empty) and /INT is set to low-active, the
interrupt output /INT is set to a low-level. The MCU verifies the buffer is empty when the D2 bit of the
status1 information is read. The MCU should write the block length data to the transmit data buffer
(FIFO) at this moment.
When a block of data is written to the transmit data buffer (FIFO), /CTS is low-level and TXEN is high-
level, the data in the transmit data buffer (FIFO) is sent to the transmit buffer. If /CTS is high-level
while data is transmitted, all data is transmitted (including the data in the transmit data buffer (FIFO)).
When the buffer becomes empty, the data in the transmit data buffer (FIFO) is not be sent to the
transmit buffer until MCU writes a new block of data to the transmit data buffer (FIFO). The MCU can
not write new data to the transmit data buffer (FIFO) until the buffer becomes empty.
Example : Block length=2
MCU
DATA DATA
Transmit data buffer(FIFO)
Transmit buffer(P S)
TxD pin
Block length=4 or more
When the transmit data buffer (FIFO) becomes empty and /INT is set low-active, the interrupt output
/INT becomes low. The MCU verifies the buffer is empty by reading the D2 bit of the status1
information.
When this happens, the MCU should write the 4-bytes of data to the transmit data buffer (FIFO). The
data in the transmit data buffer (FIFO) is sent to the transmit buffer when /CTS is low-level and TXEN
is high-level. When the number of bytes from the MCU becomes less than 4 at the last stage of the
block transmission, the same operation should be made as the block length=1~3.
When the buffer becomes empty, the data in the transmit data buffer (FIFO) is not be sent to the
transmit buffer until MCU writes data of the fixed block length to the transmit data buffer (FIFO). The
MCU cannot write data to the transmit data buffer (FIFO) until the buffer becomes empty.
REJ03F269-0100 Rev.1.00 Feb.19.2008
Page 5 of 22
5 Page 
R8A66171DD/SP
Command4
Internal reset
1 : Reset
Error reset
1 : Error flag clear
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Transmission carrier control
1 : RTS="L"
0 : RTS="H"
Wakeup mode
1 : Enable
0 : Disable
Receive enable
Transmit enable
1 : Enable
0 : Disable
1 : Enable
0 : Disable
10
IR
ER
RTS WUMODE RXEN
TXEN
D7 D6 D5 D4 D3 D2 D1 D0
Command5 (Address setting. The second byte when D2 bit of the command4 is set to “1”.)
Command5 Address setting. The second byte when D2 bit of the command4 bit is set to "1".
D7 D6 D5 D4 D3 D2 D1 D0
Command6
1 1 D5 D4 D3 D2 D1 D0
D7 D6
1 : FIFO disable
0 : FIFO enable
1 : INT
0 : INT
1 : P1=Packet transmission
is complete
0 : P1=P0
1 : P0="H"
0 : P0="L"
REJ03F269-0100 Rev.1.00 Feb.19.2008
Page 11 of 22
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet R8A66171SP.PDF ] | |
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