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PDF R8A66173SP Data sheet ( Hoja de datos )
| Número de pieza | R8A66173SP | |
| Descripción | 4-CH 12-BIT PWM GENERATOR | |
| Fabricantes | Renesas Technology | |
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R8A66173SP
4-CH 12-BIT PWM GENERATOR
REJ03F0264-0100
Rev.1.00
Jan.24.2008
DESCRIPTION
R8A66173 has four 12-bit PWM (Pulse Width Modulation) circuits which are built by using the CMOS
process.
This IC controls PWM waveform by adjusting the “H” width according to serial data sent from MCU (Micro
Controller Unit) or other device. Each channel can be independently controlled.
High-resolution digital-analog (D-A) converter can be formed easily by connecting a low-pass filter (LPF)
circuit to the output pins of this circuit.
R8A66173 is the succession product of M66242.
www.DataSheet4FU.EcomATURES
● Built-in four 12-bit high-resolution PWM circuits
● Easy D-A conversion – Quick output waveform smoothing
Control by 1.22mV possible per step (VCC=5V range)
● Serial data input
●“H” level width setting type
● 4 channels controlled independently
● All 4 channels reset by reset input (R), High-impedance status after reset
● All 4 channels controlled by output control input (OC)
● Settings take effect after ongoing cycle is completed
● Output : CMOS 3-state output
Output current Io=±4mA (Vcc=5.0V range), Io=±2mA (Vcc=3.3V range)
● Wide operating supply voltage range (Vcc=3.0~3.6V or Vcc=4.5~5.5V, single power supply)
● Wide operating temperature range: Ta=-40oC~+85 oC
APPLICATION
● Analog signal control in televisions and audio systems
● Control of lamps, heaters and motors
● For software servo in home appliances and industrial machinery
PIN CONFIGURATION (TOP VIEW)
CHIP SELECT
RESET
CS
R
WRITE CONTROL WR
SERIAL DATA INPUT SIN
WRITE CLOCK ScLK
OUTPUT CONTROL OC
GND
1
2
3
4
5
6
7
14 Vcc
13 PWM1
12 PWM2
OUTPUT
11 PWM3
10 PWM4
9
XOUT
CLOCK OUTPUT
8 XIN
CLOCK INPUT
REJ03F0264-0100 Rev.1.00 Jan.24.2008
Page 1 of 12
1 page  
R8A66173SP
PWM Waveform Output
(1)12-bit PWM output
One PWM waveform cycle is divided into 16(=24) subsections t, and each subsection is further divided
into 256(=28) minimum resolution bits τ(=2/fXIN). The “H” width of subsection t basic waveform is
determined by the upper 8-bits of PWM data. (In Fig.2 above, ”H” width is 4A16=74×τ)
Among these 16 subsections t, subsections tm designated by the lower 4-bits of PWM data have “H”
width that is longer by τ.
(In Fig.2 above, the “H” width of designated 6 subsections (m =2, 4, 6, 10, 12 and 14) is 4B16=75×τ.)
The “H” width of undesignated subsections remains unchanged.
As explained above, one cycle of waveform is a combination of two waveforms different in the “H” width.
(In Fig. 2 above, one cycle consists of 10 subsections whose “H” width is 74×τ and 6 subsections whose
“H” width is 75×τ)
Note: It is impossible to set one whole cycle to “H” level.
(2)8-bit PWM output
www.DataSheet4U.cAosmcan be seen from the 12-bit PWM waveform output process as described above, 8-bit resolution PWM
waveform can be output by fixing the lower 4-bits of PWM data to 00002.
All subsections from t0 to t15 have the “H” width as determined by the upper 8-bits of PWM data.
Note: It is impossible to set one whole cycle to “H” level.
Output Control
(1)Serial data input
By using data on lower byte register b3 (output control selection bit), output of each channel can be
controlled independently. The state of the selected PWM output changes after the completion of the
ongoing cycle.
When b3 is set 0, lower byte register b0 (write data designation bit) is reset. Do not write on upper byte in
this case.
(2)Output control input
The status of all 4-channel outputs during a cycle is determined depending on the status of output control
input OC at the start of the cycle. (See Fig. 6.)
Even when output is in a high-impedance state, data on each PWM register is retained, and data can be
rewritten.
(3)Reset
When reset input R turns “L”, all operation is reset as soon as the ongoing cycle is completed. The
outputs of all 4-channels turn high-impedance. The PWM register of each channel is reset.
When R is shifted from “L” to “H”, a next cycle starts, and data writing becomes possible. However,
outputs stay in the high-impedance state. (See Fig. 6)
To resume output, write input data for each channel.
Initial State
After power-on, outputs and PWM register data are unstable.
(1)Reset
Reset input R is kept on “L” level for more than one cycle (2.048ms when fXIN is 4 MHz) or more, this
integrated circuit is put in a reset state.
If stabilization needs more time, e.g. when a quartz resonator is used, keep R on “L” level for an
adequate period of time.
(2)Serial data input
When starting using this integrated circuit without resetting, input false lower byte data (b0=0) to stabilize
lower byte register b0 data, and then input normal data.
REJ03F0264-0100 Rev.1.00 Jan.24.2008
Page 5 of 12
5 Page 
R8A66173SP
TIMING CHARTS
tsu(CS) th(CS)
CS 50% 50%
WR
SCLK
www.DataSheet4U.coSmIN
50%
tsu(WR)
tw (S) tw (S)
50%
50%
tsu(S) th(S)
50%
50%
50%
tWRH
50%
th(WR) th(SCLK)
50%
50% 50%
tc(X)
tw (XH) tw (XL)
XIN
50%
50%
50%
Vcc
0V
Vcc
0V
Vcc
0V
Vcc
0V
Vcc
0V
(internal clock)
PWM1~4
tPLH
50%
tPHL
50%
Note 2. (1)Shaded portions indicate that switching is possible during those periods.
(2)PWM outputs 1 to 4 change synchronously with internal clock signals Φ.
The frequency of these signals is the 1/2 divider of the frequency input from XIN.
V OH
V OL
APPLICATION EXAMPLE (Combination with electronic control for amplifier system)
CD
FM
DAT
AV
Graphic
equalizer
Electronic control
Pow er amplifier
Speaker
Control microcomputer
MCU
R8A66173SP
Buffer/Low -pass filter
PWM
REJ03F0264-0100 Rev.1.00 Jan.24.2008
Page 11 of 12
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet R8A66173SP.PDF ] | |
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