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PDF R8A66597BG Data sheet ( Hoja de datos )
| Número de pieza | R8A66597BG | |
| Descripción | ASSP | |
| Fabricantes | Renesas Technology | |
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R8A66597FP/DFP/BG
ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
REJ03F0229-0101
Rev1.01
Oct 17, 2008
1 Overview
1.1 Overview
The R8A66597 is a Universal Serial Bus (USB) Controller equipped with USB Host functions and Peripheral functions
applicable for On-The-Go. When selecting the Host Controller function, it has two USB ports available for Hi-Speed,
Full-Speed, and Low-Speed transfer compliant with USB Specification Revision 2.0. When selecting the Peripheral
www.DataSheet4U.cCoomntroller function, it has one USB port available for Hi-Speed and Full-Speed transfer compliant with USB Specification
Revision 2.0.
This controller has a built-in USB transceiver and is compatible with all the transfer types defined in USB Specification
Revision 2.0.
The internal buffer memory is 8.5K, and a maximum ten pipes can be used for transferring data. For Pipe1 to Pipe9, any
endpoint address can be assigned matching the peripheral functions for communication or user system. Separate bus or
multiplex bus can be selected for the CPU connection. A split bus interface (exclusively for the DMA interface) that is
different from the CPU bus interface is provided and is suitable for systems demanding high-performance data transfer.
1.2 Features
1.2.1 Built-in Host Controller and Peripheral Controller compatible with Hi-Speed USB
• Built-in USB Host Controller and Peripheral Controller
• Toggle between USB Host functions and Peripheral functions is possible according to what is written to the register
• Built-in USB transceiver
1.2.2 Low power consumption
• 1.5V core power consumes less power when operating
• With the installed Low Power Sleep Mode functions, less power is consumed when the USB is not in use, which is
also applicable for portable devices
• Standby power consumption can be greatly reduced by keeping only the VIF power source ON when not using the
USB function.
• Operational with a 3.3V single power supply using the internal 1.5V core power regulator
1.2.3 Space-saving package
• Few external devices and space-saving package
VBUS signal can be connected directly to the controller input pin
Built-in D+ pull-up resistor (for Peripheral function)
Built-in D+ and D- pull-down resistors (for Host function)
Built-in D+ and D- terminating resistors (for Hi-Speed operations)
Built-in D+ and D- output resistors (for Full-Speed and Low-Speed operations)
Rev1.01 Oct 17, 2008
page 1 of 183
1 page  
R8A66597FP/DFP/BG
R8A66597BG
( TOP VIEW )
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A GND
D15
D14
D10
GND
D5/AD5 D2/AD2
D0
GND A
B VIF
INT_N
D13
D11
VIF
D4/AD4 D1/AD1
CS_N
VIF B
www.DataSheet4U.com C DREQ0_N DACK0_N SOF_N
D9
D7/AD7 D3/AD3 WR1_N W R0_N
RD_N C
D DREQ1_N DACK1_N DEND0_N
D12
D8 D6/AD6 A6
A4
A5 D
E GND
VDD DEND1_N SD0
GND
A7/ALE
A3
VD D
GND E
F SD2
SD3
SD4
SD1
VB OUT0
A2
GND
MPBUS
A1 F
G SD5
SD6
AVCC VBOUT1 OVCUR1 EXTLP0
ID0
R ST_N
VCC G
H VIF
SD7
XIN
AGND
VCC OVCUR0B OVCUR0A GND
VBUS H
J GND
1
VCC
2
XO UT
3
RE FRIN
4
DM1
5
DP1
6
GND
7
D M0
8
DP0
9
J
The “_N” in the signal
name indicates that the
signal is in the “L” active
Package
R8A66597BG : PLBG0081KA-A : 81pinLFBGA (0.5mm pitch)
Figure 1.2 R8A66597BG Pin Layout
Rev1.01 Oct 17, 2008 Page 5 of 183
Confidential
5 Page 
R8A66597FP/DFP/BG
1.6.4
USB data transfer
All types of data transfer of USB communication, such as control transfer, bulk transfer, interrupt transfer and
isochronous transfer, are possible with this controller. The following are the pipe resources for each transfer type:
(1) Control transfer dedicated pipe - 1
(2) Interrupt transfer dedicated pipes - 4
(3) Bulk transfer dedicated pipes - 3
(4) Bulk transfer or isochronous transfer selection pipes - 2
Write the USB transfer requirements for each pipe, such as transfer type, endpoint address, maximum packet size,
etc., according to the user system. This controller is equipped with an 8.5KB buffer memory. Allocate the buffer
memory according to the user system or execute the settings such as buffer operation mode, for the bulk transfer
dedicated pipe, and bulk transfer or isochronous transfer selection pipe. In buffer operations mode, high-performance
www.DataSheet4U.codmata transfer with low interrupt frequency is possible by using a double buffer configuration or continuous transfer
function of the data packet. A transfer completion function has been added, using the transaction counter function for
efficient data transfer rates of bulk and isochronous transfer pipes.
The user system control CPU and DMA controller access the buffer memory through three FIFO port registers.
1.6.5
Interface for access from DMAC
The DMA interface is the data transfer between the user system and this controller, in which the DxFIFO port is used,
and it is a data transfer that does not use the CPU. This controller is equipped with 2-ch DMA interface and includes
the following functions:
(1) Transfer end notification function corresponding to the transfer end signal (DEND signal)
(2) FIFO buffer auto clear function while receiving a zero-length packet
This controller is equipped with an interface compatible with the two types of DMA transfers given below:
(1) Cycle Steal Transfer
Assert and negate of the DREQ pin is repeatedly transmitted for one data transmission (1 byte/1 word).
(2) Burst Transmission
This is a transmission in which the DREQ pin is asserted (not negated) until the transmission is completed, due to
the pipe buffer memory area allocated to the FIFO port or DEND signal.
"CS_N, RD_N and WR_N" or DACK_N can be selected as the handshake signal (pin) of the DMA interface.
High-performance DMA transmission is possible in the DMA transmission by a split bus by modifying the data setup
timing using an OBUS bit operation of the DMAxCFG register.
1.6.6
SOF pulse output function
This controller is equipped with an SOF pulse output function that notifies the SOF packet send/receive timing. When
the Host Controller function is selected, a pulse is output from the SOF_N pin at sending the SOF packet. When the
Peripheral Controller function is selected, a pulse is output from the SOF_N pin at receiving the SOF packet. When the
SOF packet is damaged, a pulse is output within the specified period according to the SOF interpolation timer.
Rev1.01 Oct 17, 2008 Page 11 of 183
Confidential
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