PDF AS7C33128NTD18B Data sheet ( Hoja de datos )

Número de pieza	AS7C33128NTD18B
Descripción	3.3V 128Kx18 Pipelined SRAM
Fabricantes	Alliance Semiconductor Corporation
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No Preview Available ! April 2005 AS7C33128NTD18B ® 3.3V 128K×18 Pipelined SRAM with NTDTM Features • Organization: 131,072 words × 18 bits • NTD™ architecture for efficient bus operation • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous operation • Asynchronous output enable control www.DataShee•t4AUv.caoimlable in 100-pin TQFP package • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ • Self-timed write cycles • Interleaved or linear burst modes • Snooze mode for standby operation Logic block diagram A[16:0] 17 CE0 CE1 CE2 R/W BWa BWb ADV / LD LBO ZZ DBAruedrgsditsrletoesgrsicQ CLK Control logic CLK DQ [a:b] 18 DRIDneapgtuiastterQ CLK CLK CEN 17 17 DQ Write delay addr. registers CLK 17 CLK 128K x 18 SRAM Array 18 18 18 18 CLK Output OE Register 18 OE DQ [a:b] Selection Guide Minimum cycle time Maximum clock frequency Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) -200 -166 -133 Units 5 6 7.5 ns 200 166 133 MHz 3.0 3.5 4 ns 375 350 325 mA 135 120 110 mA 30 30 30 mA 4/28/05; v.1.3 Alliance Semiconductor P. 1 of 19 Copyright © Alliance Semiconductor. All rights reserved. 1 page AS7C33128NTD18B ® Signal descriptions Signal I/O Properties Description CLK I CLOCK Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock. CEN I SYNC Clock enable. When de-asserted HIGH, the clock input signal is masked. A, A0, A1 I SYNC Address. Sampled when all chip enables are active and ADV/LD is asserted. DQ[a,b] I/O SYNC Data. Driven as output when the chip is enabled and OE is active. CE0, CE1, CE2 www.DataSheet4U.com ADV/LD I I SYNC SYNC Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted. Are ignored when ADV/LD is HIGH. Advance or Load. When sampled HIGH, the internal burst address counter will increment in the order defined by the LBO input value. When LOW, a new address is loaded. R/W I SYNC A HIGH during LOAD initiates a READ operation. A LOW during LOAD initiates a WRITE operation. Is ignored when ADV/LD is HIGH. BW[a,b] I SYNC Byte write enables. Used to control write on individual bytes. Sampled along with WRITE command and BURST WRITE. OE I ASYNC Asynchronous output enable. I/O pins are not driven when OE is inactive. LBO Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst I STATIC order. When driven Low, device follows linear Burst order. This signal is internally pulled High. ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused. NC - - No connects. Snooze Mode SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of SNOOZE MODE is dictated by the length of time the ZZ is in a High state. The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE. When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE. Burst order Interleaved burst order (LBO = 1) A1 A0 A1 A0 A1 A0 Starting address 0 0 0 1 1 0 First increment 01 00 11 Second increment 1 0 1 1 0 0 Third increment 1 1 1 0 0 1 A1 A0 11 10 01 00 Linear burst order (LBO = 0) A1 A0 A1 A0 A1 A0 Starting Address 0 0 0 1 1 0 First increment 01 10 11 Second increment 1 0 1 1 0 0 Third increment 1 1 0 0 0 1 A1 A0 11 00 01 10 4/28/05; v.1.3 Alliance Semiconductor P. 5 of 19 5 Page Timing waveform of write cycle CLK tCES tCEH CEN www.DataSheet4U.com Address tAS tAH A1 A2 ® tCH tCL AS7C33128NTD18B tCYC A3 R/W BWn CE0,CE2 tCSH CE1 ADV/LD tADVS tADVH OE Din Dout Q(n-2) D(A1) tHZOE Q(n-1) D(A2) D(A2Y‘01) tDS tDH D(A3) D(A2Y‘10) D(A2Y‘11) Write D(A1) DSEL Write D(A2) Continue Continue Continue Write Write Write D(A2Y‘01) D(A2Y‘10) D(A2Y‘11) Inhibit Clock Write D(A3) Continue Write D(A3Y‘01) 4/28/05; v.1.3 Alliance Semiconductor P. 11 of 19 11 Page

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