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PDF AS7C33128PFS32B Data sheet ( Hoja de datos )
| Número de pieza | AS7C33128PFS32B | |
| Descripción | (AS7C33128PFS32B / AS7C33128PFS36B) 3.3V 128K X 32/36 pipeline burst synchronous SRAM | |
| Fabricantes | Alliance Semiconductor Corporation | |
| Logotipo |  |
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March 2002
AS7C33128PFS32A
AS7C33128PFS36A
®
3.3V 128K X 32/36 pipeline burst synchronous SRAM
Features
• Organization: 131,072 words × 32 or 36 bits
• Fast clock speeds to 200 MHz in LVTTL/LVCMOS
• Fast clock to data access: 3.0/3.1/3.5/4.0/5.0 ns
• Fast OE access time: 3.0/3.1/3.5/4.0/5.0 ns
• Fully synchronous register-to-register operation
• Single register “Flow-through” mode
• Single-cycle deselect
www.DataShee•t4DUu.caolm-cycle deselect also available (AS7C33128PFD32A/
AS7C33128PFD36A)
• Pentium®1 compatible architecture and timing
• Asynchronous output enable control
• Economical 100-pin TQFP package
• Byte write enables
• Multiple chip enables for easy expansion
• 3.3 core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• 30 mW typical standby power in power down mode
• NTD™1 pipeline architecture available
(AS7C33128NTD32A/ AS7C33128NTD36A)
1 Pentium® is a registered trademark of Intel Corporation. NTD™ is a
trademark of Alliance Semiconductor Corporation. All trademarks
mentioned in this document are the property of their respective owners.
Logic block diagram
Pin arrangement
CLK
ADV
ADSC
ADSP
A[16:0]
GWE
BWE
BWd
BWc
BWb
BWa
CE0
CE1
CE2
ZZ
OE
LBO
CLK
CE
Q0
Burst logic
CLR
17 D
Q1 128K × 32/36
Q 17 15 17
Memory
array
CE
Address
register
CLK
D DQd Q
Byte write
registers
CLK
D DQc Q
Byte write
registers
CLK
D DQb Q
Byte write
registers
CLK
D DQa Q
Byte write
registers
CLK
36/32
36/32
4
Power
down
DQ
Enable
CE register
CLK
D Enable Q
delay
register
CLK
OE
Output
registers
CLK
Input
registers
CLK
36/32
FT DQ [a:d]
DQPc/NC
DQc
DQc
VDDQ
VSSQ
DQc
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
FT
VDD
NC
VSS
DQd
DQd
VDDQ
VSSQ
DQd
DQd
DQd
DQd
VSSQ
VDDQ
DQd
DQd
DQPd/NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
TQFP 14 × 20 mm
80 DQPb/NC
79 DQb
78 DQb
77 VDDQ
76 VSSQ
75 DQb
74 DQb
73 DQb
72 DQb
71 VSSQ
70 VDDQ
69 DQb
68 DQb
67 VSS
66 NC
65 VDD
64 ZZ
63 DQa
62 DQa
61 VDDQ
60 VSSQ
59 DQa
58 DQa
57 DQa
56 DQa
55 VSSQ
54 VDDQ
53 DQa
52 DQa
51 DQPa/NC
Note: Pins 1,30,51,80 are NC for ×32
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
–200
5
200
3
570
160
30
–183
5.4
183
3.1
540
140
30
–166
6
166
3.5
475
130
30
–133
7.5
133
4
425
100
30
–100
10
100
5
325
90
30
Units
ns
MHz
ns
mA
mA
mA
3/4/02; v.1.4
Alliance Semiconductor
P. 1 of 13
Copyright © Alliance Semiconductor. All rights reserved.
1 page  
AS7C33128PFS32A
AS7C33128PFS36A
®
Recommended operating conditions
Parameter
Symbol
Min Nominal
Supply voltage
3.3V I/O supply voltage
2.5V I/O supply voltage
www.DataSheet4U.com
Input voltages1
Address and
control pins
I/O pins
Ambient operating temperature
VDD
VSS
VDDQ
VSSQ
VDDQ
VSSQ
VIH
VIL
VIH
VIL
TA
3.135
0.0
3.135
0.0
2.35
0.0
2.0
–0.52
2.0
–0.52
0
3.3
0.0
3.3
0.0
2.5
0.0
–
–
–
–
–
1 Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications.
2 VIL min. = –2.0V for pulse width less than 0.2 × tRC.
TQFP thermal resistance
Description
Conditions
Thermal resistance
(junction to ambient)1
Thermal resistance
(junction to top of case)1
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per EIA/
JESD51
1 This parameter is sampled.
Symbol
θJA
θJC
Max
3.6
0.0
3.6
0.0
2.9
0.0
VDD + 0.3
0.8
VDDQ + 0.3
0.8
70
Unit
V
V
V
V
V
°C
Typical
46
2.8
Units
°C/W
°C/W
3/4/02; v.1.4
Alliance Semiconductor
P. 5 of 13
5 Page 
AS7C33128PFS32A
AS7C33128PFS36A
®
AC test conditions
• Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C.
• Input pulse level: GND to 3V. See Figure A.
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
Thevenin equivalent:
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
www.DataSheet4U+.c3o.m0V 90%
10%
GND
90%
10%
DOUT
Z0 = 50Ω
50Ω
VL = 1.5V
for 3.3V I/O;
30 pF* = VDDQ/2
for 2.5V I/O
DOUT
353Ω / 1538Ω
319Ω / 1667Ω
5 pF*
GND *including scope
and jig capacitance
Figure A: Input waveform
Figure B: Output load (A)
Figure C: Output load (B)
Notes
1 For test conditions, see AC Test Conditions, Figures A, B, C.
2 This parameter measured with output load condition in Figure C.
3 This parameter is sampled, but not 100% tested.
4 tHZOE is less than tLZOE; and tHZC is less than tLZC at any given temperature and voltage.
5 tCH measured as HIGH above VIH and tCL measured as LOW below VIL.
6 This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet
the setup and hold times for all rising edges of CLK when chip is enabled.
7 Write refers to GWE, BWE, BW[a:d].
8 Chip select refers to CE0, CE1, CE2.
Package Dimensions
100-pin quad flat pack (TQFP)
TQFP
Min Max
A1 0.05 0.15
A2 1.35 1.45
b 0.22 0.38
c 0.09 0.20
D
13.90
14.10
E
19.90
20.10
e 0.65 nominal
Hd
15.90
16.10
He
21.90
22.10
L 0.45 0.75
L1 1.00 nominal
α 0° 7°
Dimensions in millimeters
Hd
D
He E
b
e
α
c
L1
L
A1 A2
3/4/02; v.1.4
Alliance Semiconductor
P. 11 of 13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet AS7C33128PFS32B.PDF ] | |
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| AS7C33128PFS32B | (AS7C33128PFS32B / AS7C33128PFS36B) 3.3V 128K X 32/36 pipeline burst synchronous SRAM | Alliance Semiconductor Corporation |
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