PDF AS7C33256FT36A Data sheet ( Hoja de datos )

Número de pieza	AS7C33256FT36A
Descripción	(AS7C33256FT32A / AS7C33256FT36A) 3.3V 256K x 32/36 Flow-through synchronous SRAM
Fabricantes	Alliance Semiconductor Corporation
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No Preview Available ! November 2004 AS7C33256FT32A AS7C33256FT36A ® 3.3V 256K × 32/36 Flow-through synchronous SRAM Features • Organization: 262,144 words × 32 or 36 bits • Fast clock to data access: 7.5/8.5/10 ns • Fast OE access time: 3.5/4.0/4.0 ns • Fully synchronous flow-through operation • Asynchronous output enable control • Available in 100-pin TQFP package • Individual byte write and global write www.DataSheet4U.com • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ • Linear or interleaved burst control • Snooze mode for reduced power-standby • Common data inputs and data outputs Logic block diagram CLK ADV ADSC ADSP A[17:0] GWE BWE BWd BWc BWb BWa CE0 CE1 CE2 ZZ OE 18 Power down LBO CLK CE CLR Q0 Burst logic Q1 DQ CCELKAredgdisrteesrs 18 2 16 D BytDeQwdriteQ registers CLK DBytDeQwcriteQ registers CLK DBytDeQwbriteQ registers CLK DBytDeQwariteQ registers CLK DQ Enable CE register CLK D Enable Q redgeilsatyer CLK 256K × 32/36 2 Memory array 18 32/36 32/36 4 OE Output registers CLK Input registers CLK 32/36 DQ[a:d] Selection guide Minimum cycle time Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) -75 -85 8.5 10 7.5 8.5 300 275 110 100 30 30 -10 12 10 250 90 30 Units ns ns mA mA mA 11/30/04, v 1.1 Alliance Semiconductor 1 of 19 Copyright © Alliance Semiconductor. All rights reserved. 1 page AS7C33256FT32A AS7C33256FT36A ® Signal descriptions Pin CLK A,A0,A1 DQ[a,b,c,d] CE0 CE1, CE2 www.DataSheet4U.com ADSP ADSC ADV GWE BWE BW[a,b,c,d] OE LBO ZZ NC I/O Properties Description I CLOCK Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock. I SYNC Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted. I/O SYNC Data. Driven as output when the chip is enabled and when OE is active. I SYNC Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive, ADSP is blocked. Refer to the “Synchronous truth table” for more information. I SYNC Synchronous chip enables, active high, and active low, respectively. Sampled on clock edges when ADSC is active or when CE0 and ADSP are active. I SYNC Address strobe processor. Asserted low to load a new address or to enter standby mode. I SYNC Address strobe controller. Asserted low to load a new address or to enter standby mode. I SYNC Advance. Asserted low to continue burst read/write. I SYNC Global write enable. Asserted low to write all 32/36 bits. When high, BWE and BW[a:d] control write enable. I SYNC Byte write enable. Asserted low with GWE high to enable effect of BW[a:d] inputs. Write enables. Used to control write of individual bytes when GWE is high and BWE is low. If any of I SYNC BW[a:d] is active with GWE high and BWE low, the cycle is a write cycle. If all BW[a:d] are inactive, the cycle is a read cycle. I ASYNC Asynchronous output enable. I/O pins are driven when OE is active and chip is in read mode. I STATIC Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When driven Low, device follows linear Burst order. This signal is internally pulled High. I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused. - - No connect Snooze Mode SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of SNOOZE MODE is dictated by the length of time the ZZ is in a High state. The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE. When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE. 11/30/04, v 1.1 Alliance Semiconductor 5 of 19 5 Page Key to switching waveforms ® Rising input Falling input don’t care Timing waveform of read cycle CLK tCYC tCH tCL www.DataSheet4U.com tADSPS ADSP ADSC tADSPH tADSCS tADSCH tAS tAH Address A1 A2 GWE, BWE tWS tWH tCSS CE0, CE2 tCSH LOAD NEW ADDRESS A3 CE1 ADV OE tADVS tADVH ADV inserts wait states AS7C33256FT32A AS7C33256FT36A Undefined Dout tOE tLZOE Q(A1) tHZOE tOH Q(A2Ý01) Q(A2Ý10) Q(A2Ý11) Q(A3) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11) tCD tHZC Read Q(A1) Suspend Read Q(A1) Read Burst Burst Suspend Burst Read Burst Burst Burst Q(A2) Read Read Read Read Q(A3) Read Read Read DSEL Q(A 2Ý01) Q(A 2Ý10) Q(A 2Ý10) Q(A 2Ý11) Q(A 3Ý01) Q(A 3Ý10) Q(A 3Ý11) Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care. 11/30/04, v 1.1 Alliance Semiconductor 11 of 19 11 Page

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