PDF AS7C33256NTD36A Data sheet ( Hoja de datos )

Número de pieza	AS7C33256NTD36A
Descripción	(AS7C33256NTD32A / AS7C33256NTD36A) 3.3V 256K x 2/36 Pipelined burst Synchronous SRAM
Fabricantes	Alliance Semiconductor Corporation
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No Preview Available ! November 2004 AS7C33256NTD32A AS7C33256NTD36A ® 3.3V 256K×32/36 Pipelined burst Synchronous SRAM with NTDTM Features • Organization: 262,144 words × 32 or 36 bits • NTD™architecture for efficient bus operation • Fast clock speeds to 166 MHz • Fast clock to data access: 3.5/4.0 ns • Fast OE access time: 3.5/4.0 ns • Fully synchronous operation • Common data inputs and data outputs www.DataShee•t4AUs.cyonmchronous output enable control • Available in 100-pin TQFP • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion • 3.3 core power supply • 2.5V or 3.3V I/O operation with separate VDDQ • Self-timed write cycles • Interleaved or linear burst modes • Snooze mode for standby operation Logic Block Diagram A[17:0] 18 CE0 CE1 CE2 R/W BWa BWb BWc BWd ADV / LD LBO ZZ DQ [a:d] 36/32 DBAruedrgsditsrletoesgrsQic CLK Cloongtircol CLK DRIDneapgtuiastteQr CLK 18 DQ Write delay addr. registers CLK 18 CLK 36/32 256K x 32/36 SRAM Array 36/32 36/32 CLK CEN Selection Guide Minimum cycle time Maximum clock frequency Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 36/32 CLK Output Register OE 36/32 OE DQ[a:d] -166 -133 6 7.5 166 133 3.5 4 475 400 130 100 30 30 Units ns MHz ns mA mA mA 11/30/04, v. 2.1 Alliance Semiconductor P. 1 of 19 Copyright © Alliance Semiconductor. All rights reserved. 1 page AS7C33256NTD32A AS7C33256NTD36A ® Signal descriptions Signal I/O Properties Description CLK I CLOCK Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock. CEN I SYNC Clock enable. When de-asserted high, the clock input signal is masked. A, A0, A1 I SYNC Address. Sampled when all chip enables are active and ADV/LD is asserted. DQ[a,b,c,d] I/O SYNC Data. Driven as output when the chip is enabled and OE is active. CE0, CE1, CE2 I SYNC Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted. Are ignored when ADV/LD is high. www.DataSheet4AUD.cVom/LD Advance or Load. When sampled high, the internal burst address counter will increment in I SYNC the order defined by the LBO input value. (refer to table on page 2) When low, a new address is loaded. R/W I SYNC A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE operation. Is ignored when ADV/LD is high. BW[a,b,c,d] I SYNC Byte write enables. Used to control write on individual bytes. Sampled along with WRITE command and BURST WRITE. OE I ASYNC Asynchronous output enable. I/O pins are not driven when OE is inactive. LBO Selects Burst mode. When tied to VDD or left floating, device follows Interleaved Burst I STATIC order. When driven Low, device follows linear Burst order. This signal is internally pulled High. ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused. NC - - No connect. Note that pin 84 will be used for future address expansion to 16Mb density. Snooze Mode SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of SNOOZE MODE is dictated by the length of time the ZZ is in a High state. The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE. When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE. 11/30/04, v. 2.1 Alliance Semiconductor P. 5 of 19 5 Page Key to switching waveforms Rising input Timing waveform of read cycle CLK www.DataSheet4U.com tCES tCEH Falling input tCH tCL ® don’t care CEN Address tAS tAH A1 tWS tWH R/W tWS tWH BWn CE0,CE2 tCSH A2 CE1 ADV/LD tADVS tADVH AS7C33256NTD32A AS7C33256NTD36A Undefined tCYC A3 OE Dout 11/30/04, v. 2.1 tOE tLZOE tHZOE Q(A1) Q(A2) Q(A2Y‘10) Read Q(A1) DSEL Read Q(A2) Q(A2Y‘01) Continue Continue Continue Read Read Read Q(A2Y‘01) Q(A2Y‘10) Q(A2Y‘11) Inhibit Clock tHLZC Q(A3) Q(A2Y‘11) Read Q(A3) Continue Read Q(A3Y‘01) Alliance Semiconductor P. 11 of 19 11 Page

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Número de pieza	Descripción	Fabricantes
AS7C33256NTD36A	(AS7C33256NTD32A / AS7C33256NTD36A) 3.3V 256K x 2/36 Pipelined burst Synchronous SRAM	Alliance Semiconductor Corporation

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