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PDF LTC2351-14 Data sheet ( Hoja de datos )
| Número de pieza | LTC2351-14 | |
| Descripción | 1.5Msps Simultaneous Sampling ADC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC2351-14 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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FEATURES
■ 1.5Msps ADC with 6 Simultaneously Sampled
Differential Inputs
■ 250ksps Throughput per Channel
■ 75dB SINAD
■ Low Power Dissipation: 16.5mW
www.DataSh■eet34UV.cSoimngle Supply Operation
■ 2.5V Internal Bandgap Reference, Can be Overdriven
with External Reference
■ 3-Wire SPI-Compatible Serial Interface
■ Internal Conversion Triggered by CONV
■ SLEEP (12µW) Shutdown Mode
■ NAP (4.5mW) Shutdown Mode
■ 0V to 2.5V Unipolar, or ±1.25V Bipolar Differential
Input Range
■ 83dB Common Mode Rejection
■ Tiny 32-Pin (5mm × 5mm) QFN Package
U
APPLICATIO S
■ Multiphase Power Measurement
■ Multiphase Motor Control
■ Data Acquisition Systems
■ Uninterruptable Power Supplies
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 6084440, 6522187.
LTC2351-14
6 Channel, 14-Bit, 1.5Msps
Simultaneous Sampling ADC
DESCRIPTIO with Shutdown
The LTC®2351-14 is a 14-bit, 1.5Msps ADC with six
simultaneously sampled differential inputs. The device
draws only 5.5mA from a single 3V supply, and comes in
a tiny 32-pin (5mm × 5mm) QFN package. A SLEEP
shutdown mode further reduces power consumption to
12µW. The combination of low power and tiny package
makes the LTC2351-14 suitable for portable applications.
The LTC2351-14 contains six separate differential inputs
that are sampled simultaneously on the rising edge of the
CONV signal. These six sampled inputs are then
converted at a rate of 250ksps per channel.
The 83dB common mode rejection allows users to
eliminate ground loops and common mode noise by
measuring signals differentially from the source.
The device converts 0V to 2.5V unipolar inputs differen-
tially, or ±1.25V bipolar inputs also differentially,
depending on the state of the BIP pin. Any analog input
may swing rail-to-rail as long as the differential input
range is maintained.
The conversion sequence can be abbreviated to convert
fewer than six channels, depending on the logic state of
the SEL2, SEL1 and SEL0 inputs.
The serial interface sends out the six conversion results in
96 clocks for compatibility with standard serial interfaces.
BLOCK DIAGRA
CH5– CH5+
21 20 19
CH4– CH4+
18 17 16
CH3–
15
CH3+
14 12
13
CH2– CH2+
11 10 9
CH1– CH1+
8 76
CH0– CH0+
54
–
S AND H
–
S AND H
–
S AND H
–
S AND H
–
S AND H
–
S AND H
MUX
2.5V
REFERENCE
10µF
3V
VCC VDD
24 25
1.5Msps
14-BIT ADC
14-BIT LATCH 0
14-BIT LATCH 1
14-BIT LATCH 2
14-BIT LATCH 3
14-BIT LATCH 4
14-BIT LATCH 5
TIMING
LOGIC
33 22
23 29
GND 10µF VREF BIP
26 27 28
SEL2 SEL1 SEL0
THREE-
STATE
SERIAL
OUTPUT
PORT
OVDD
3V
3
SD0
1
OGND
2
CONV
30
SCK
32
DGND
31
235114 TA01
0.1µF
235114f
1
1 page  
TYPICAL PERFOR A CE CHARACTERISTICS VDD = 3V, TA = 25°C
LTC2351-14
SINAD vs Input Frequency
77
74
71
68
65
www.DataSheet4U.com
62
59
56
0.1
1
FREQUENCY (MHz)
10
235114 G01
SFDR vs Input Frequency
92
86
80
74
68
62
56
50
0.1
1
FREQUENCY (MHz)
10
235114 G04
THD, 2nd and 3rd vs Input Frequency
–50
UNIPOLAR SINGLE-ENDED
–56
–62
THD
–68
–74 2nd
–80
–86 3rd
–92
–98
–104
–110
0.1
1
FREQUENCY (MHz)
10
235114 G02
SNR vs Input Frequency
77
74
71
68
65
62
59
56
0.1
1
FREQUENCY (MHz)
10
235114 G05
THD, 2nd and 3rd vs Input Frequency
–50
BIPOLAR SINGLE-ENDED
–56
–62 THD
–68
–74 2nd
–80
–86
–92 3rd
–98
–104
–110
0.1
1
FREQUENCY (MHz)
10
235114 G03
100kHz Unipolar Sine Wave
8192 Point FFT Plot
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
25 50 75 100
FREQUENCY (kHz)
125
235114 G06
100kHz Bipolar Sine Wave
8192 Point FFT Plot
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
25 50 75 100
FREQUENCY (kHz)
125
235114 G07
Differential Linearity vs Output Code,
Unipolar Mode
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
0
4096
8192
12288 16384
OUTPUT CODE
235114 G08
Integral Linearity vs Output Code,
Unipolar Mode
4
3
2
1
0
–1
–2
–3
–4
0
4096
8192
12288
OUTPUT CODE
16384
235114 G09
235114f
5
5 Page 
TI I G DIAGRA S
SCK
CONV
t1
Nap Mode and Sleep Mode Waveforms
NAP
www.DataSheet4USL.cEoEPm
VREF
NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS
t1
t11
LTC2351-14
235114 TD02
SCK to SDO Delay
SCK
t8
t10
SDO
VIH SCK
VOH
SDO
VOL
VIH
t9
Hi-Z
235114 TD03
235114f
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LTC2351-14.PDF ] | |
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