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PDF H5TQ1G83AFP-xxC Data sheet ( Hoja de datos )
| Número de pieza | H5TQ1G83AFP-xxC | |
| Descripción | (H5TQ1Gx3AFP-xxC) DDR3 SDRAM - 1Gb | |
| Fabricantes | Hynix Semiconductor | |
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H5TQ1G43AFP-xxC
H5TQ1G83AFP-xxC
H5TQ1G63AFP-xxC
www.DataSheet4U.com
1Gb DDR3 SDRAM
(Preliminary version)
H5TQ1G43AFP-xxC
H5TQ1G83AFP-xxC
H5TQ1G63AFP-xxC
** Since DDR3 Specification has not been defined completely yet
in JEDEC, this document may contain items under discussion.
** Contents may be changed at any time without any notice.
Rev. 0.1 / Nov 2007
This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
1
1 page  
H5TQ1G43AFP-xxC
H5TQ1G83AFP-xxC
H5TQ1G63AFP-xxC
DESCRIPTION
Preliminary The H5TQ1G43AFP-xxC, H5TQ1G83AFP-xxC and H5TQ1G63AFP-xxC are a 1,073,741,824-bit CMOS Double
Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory
density and high bandwidth. Hynix 1Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and
falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges
www.DataSheoeft4thUe.cComK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
1.1 Device Features and Ordering Information
. FEATURES
• VDD=VDDQ=1.5V +/- 0.075V
• Fully differential clock inputs (CK, /CK) operation
• Differential Data Strobe (DQS, /DQS)
• On chip DLL align DQ, DQS and /DQS transition with CK
transition
• DM masks write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data,
data strobes and data masks latched on the
rising edges of the clock
• Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11)
supported
• Programmable additive latency 0, CL-1, and CL-2
supported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• BL switch on the fly
• 8banks
• 8K refresh cycles /64ms
• JEDEC standard 78ball FBGA(x4/x8) , 96ball FBGA(x16)
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• Auto Self Refresh supported
• On Die Thermal Sensor supported ( JEDEC optional )
• 8 bit pre-fetch
. ORDERING INFORMATION
Part No.
H5TQ1G43AFP-xx*C
H5TQ1G83AFP-xx*C
H5TQ1G63AFP-xx*C
Configuration
256M x 4
128M x 8
64M x 16
Package
78ball FBGA
96ball FBGA
* XX means Binning grade (Speed/IDD...)
. OPERATING FREQUENCY
Grade
-S5
-S6
-G7
-G8
-H8
-H9
CL5
Frequency [MHz]
CL6 CL7 CL8 CL9 CL10
Remark
(CL-tRCD-tRP)
DDR3-800 5-5-5
DDR3-800 6-6-6
DDR3-1066 7-7-7
DDR3-1066 8-8-8
DDR3-1333 8-8-8
DDR3-1333 9-9-9
Rev. 0.1 /Nov 2007
5
5 Page 
H5TQ1G43AFP-xxC
H5TQ1G83AFP-xxC
H5TQ1G63AFP-xxC
Function
CKE
Abbrev
iation
Previ
ous
Curre
nt
CS#
RAS#
CAS#
WE#
BA0- A13-
BA3 A15
A12-
BC#
A10-
AP
A0-
A9,
A11
Notes
Cycle Cycle
Power Down Exit
PDX
L
LH
H
HV
HH
V V V V V 6,12
VV
ZQ Calibration Long ZQCL H
HLH
H LXXX HX
ZQ Calibration Short ZQCS H
HLH
H LXXX LX
Notes:
www.DataSheet4U.com
1. All DDR3 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE# and CKE at the rising edge of the
clock. The MSB of BA, RA and CA are device density and configuration dependant.
2. RESET# is Low enable command which will be used only for asynchronous reset so must be maintained HIGH during
any function.
3. Bank addresses (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode
Register.
4. “V” means “H or L (but a defined logic level)” and “X” means either “defined or undefined (like floating) logic level”.
5. Burst reads or writes cannot be terminated or interrupted and Fixed/on the Fly BL will be defined by MRS.
6. The Power Down Mode does not perform any refresh operation.
7. The state of ODT does not affect the states described in this table. The ODT function is not available during Self
Refresh.
8. Self Refresh Exit is asynchronous.
9. VREF(Both VrefDQ and VrefCA) must be maintained during Self Refresh operation.
10. The No Operation command should be used in cases when the DDR3 SDRAM is in an idle or wait state. The purpose
of the No Operation command (NOP) is to prevent the DDR3 SDRAM from registering any unwanted commands
between operations. A No Operation command will not terminate a previous operation that is still executing, such as
a burst read or write cycle.
11. The Deselect command performs the same function as No Operation command.
12. Refer to the CKE Truth Table for more detail with CKE transition.
Rev. 0.1 /Nov 2007
11
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