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PDF AT40KAL Data sheet ( Hoja de datos )
| Número de pieza | AT40KAL | |
| Descripción | Military Reprogrammable FPGAs | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Funcwtiwown.aDllaytaaSnhdeePt4inU.Ccoommpatible with the Atmel Rad Hard AT40KAL Series
• Ultra High Performance
– System Speeds to 85 MHz
– Array Multipliers > 45 MHz
– 14 ns Flexible SRAM
– Internal Tri-state Capability in Each Cell
• FreeRAM™
– Flexible, Single/Dual Port, Sync/Async 14 ns SRAM
– 18432 Bits of Distributed SRAM Independent of Logic Cells for AT40KAL
• 384 PCI Compliant I/Os
– Programmable Output Drive
– Fast, Flexible Array Access Facilitates Pin Locking
• 8 Global Clocks
– Fast, Low Skew Clock Distribution
– Programmable Rising/Falling Edge Transitions
– Distributed Clock Shutdown Capability for Low Power Management
– Global Reset/Asynchronous Reset Options
– 4 Additional Dedicated PCI Clocks
• Cache Logic® Dynamic Full/Partial Reconfigurability In-System
– Unlimited Reprogrammability via Serial or Parallel Modes
– Enables Adaptive Designs
– Enables Fast Vector Multiplier Updates
– Quick-Change™ Tools for Fast, Easy Design Changes
• Package Options
– MQFPF160
• Industry-standard Design Tools
– Seamless Integration (Libraries, Interface, Full Back-annotation) with Exemplar™,
Mentor®, Synplicity®
– Timing Driven Placement & Routing
– Automatic/Interactive Multi-chip Partitioning
– Fast, Efficient Synthesis
– Over 75 Automatic Component Generators Create 1000s
of Reusable, Fully Deterministic Logic and RAM Functions
• Intellectual Property Cores
– Fir Filters, UARTs, PCI, FFT and Other System Level Functions
• Easy Migration to Atmel Gate Arrays for High Volume Production
• Supply Voltage 3.3V
• Design Tools
– ATDH40M: Mother Board
– ATDH40D160M: Daughter Board for MQFPF160
– ATDS2100PC: IDS Software Design Kit
– ATDH 2225: AT17 Series Configuration Memory ISP Downloadable
• QML Q Quality Grade
Military
Reprogrammable
FPGAs with
FreeRAM™
AT40KAL
Preliminary
Rev. 4263B–AERO–06/03
1
1 page  
www.DataSheet4U.com
AT40KAL
Figure 2. Floorplan (Representative Portion)(1)
RV = Vertical Repeater
RH = Horizontal Repeater
= Core Cell
RAM RV RV RV RV RAM RV RV RV RV RAM RV RV RV RV RAM
RH RH RH RH
RH RH RH RH
RH RH RH RH
RH RH RH RH
RAM RV RV RV RV RAM RV RV RV RV RAM RV RV RV RV RAM
RH RH RH RH
RH RH RH RH
RH RH RH RH
RH RH RH RH
RAM RV RV RV RV RAM RV RV RV RV RAM RV RV RV RV RAM
RH RH RH RH
RH RH RH RH
RH RH RH RH
RH RH RH RH
RAM RV RV RV RV RAM RV RV RV RV RAM RV RV RV RV RAM
Note:
1. Repeaters regenerate signals and can connect any bus to any other bus (all path-
ways are legal) on the same plane. Each repeater has connections to two adjacent
local-bus segments and two express-bus segments. This is done automatically using
the integrated development system (IDS) tool.
4263B–AERO–06/03
5
5 Page 
RAM
www.DataSheet4U.com
AT40KAL
32 x 4 dual-ported RAM blocks are dispersed throughout the array as shown in Figure 7.
A 4-bit Input Data Bus connects to four horizontal local buses distributed over four sec-
tor rows (plane 1). A 4-bit Output Data Bus connects to four horizontal local buses dis-
tributed over four sector rows (plane 2). A 5-bit Input Address Bus connects to five
vertical express buses in same column. A 5-bit Output Address Bus connects to five ver-
tical express buses in same column. Ain (input address) and Aout (output address)
alternate positions in horizontally aligned RAM blocks. For the left-most RAM blocks,
Aout is on the left and Ain is on the right. For the right-most RAM blocks, Ain is on the
left and Aout is tied off, thus it can only be configured as a single port. For single-ported
RAM, Ain is the READ/WRITE address port and Din is the (bi-directional) data port.
Right-most RAM blocks can be used only for single-ported memories. WEN and OEN
connect to the vertical express buses in the same column.
Figure 7. RAM Connections (One Ram Block)
CLK
CLK
CLK
4263B–AERO–06/03
CLK
Din Dout
Ain Aout
32 x 4 RAM
WEN
OEN CLK
Reading and writing of the 11 - 13 ns 32 x 4 dual-port FreeRAM are independent of
each other. Reading the 32 x 4 dual-port RAM is completely asynchronous. Latches are
transparent; when Load is logic 1, data flows through; when Load is logic 0, data is
latched. These latches are used to synchronize Write Adress, Write Enable Not, and Din
signals for a synchronous RAM. Each bit in the 32 x 4 dual-port RAM is also a transpar-
ent latch. The front-end latch and the memory latch together form an edge-triggered flip
flop. When a nibble (bit = 7) is (Write) addressed and LOAD is logic 1 and WE is logic 0,
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT40KAL.PDF ] | |
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