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AT17F080 데이터시트 PDF




ATMEL Corporation에서 제조한 전자 부품 AT17F080은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 AT17F080 기능
기능 (AT17F040 / AT17F080) FPGA Configuration Flash Memory
제조업체 ATMEL Corporation
로고 ATMEL Corporation 로고


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AT17F080 데이터시트, 핀배열, 회로
Features
Prowgwrwam.DmataaSbhleee4t4,1U9.c4o,3m04 x 1 and 8,388,608 x 1-bit Serial Memories Designed to Store
Configuration Programs for Field Programmable Gate Arrays (FPGAs)
3.3V Output Capability
5V Tolerant I/O Pins
Program Support using the Atmel ATDH2200E System or Industry Third-party
Programmers
In-System Programmable (ISP) via 2-wire Bus
Simple Interface to SRAM FPGAs
Compatible with Atmel AT40K and AT94K Devices, Altera® FLEX®, APEXDevices,
Lucent® ORCA® FPGAs, Xilinx® XC3000, XC4000, XC5200, Spartan®, Virtex® FPGAs,
Motorola® MPA1000 FPGAs
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
Low-power CMOS FLASH Process
Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC
Packages), 20-lead PLCC and 44-lead TQFP Packages
Emulation of Atmel’s AT24CXXX Serial EEPROMs
Low-power Standby Mode
Single Device Capable of Holding 4-bit Stream Files Allowing Simple System
Reconfiguration
Fast Serial Download Speeds up to 33 MHz
Endurance: 5,000 Write Cycles Typical
Green (Pb/Halide-free/RoHS Compliant) Package Options Available
FPGA
Configuration
Flash Memory
AT17F040
AT17F080
1. Description
The AT17F Series of In-System Programmable Configuration PROMs (Configurators)
provide an easy-to-use, cost-effective configuration memory for Field Programmable
Gate Arrays. The AT17F Series device is packaged in the 8-lead LAP, 20-lead PLCC,
and 44-lead TQFP, see Table 1-1. The AT17F Series Configurator uses a simple
serial-access procedure to configure one or more FPGA devices.
The AT17F Series Configurators can be programmed with industry-standard program-
mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.
Table 1-1. AT17F Series Packages
Package
AT17F040
8-lead LAP
Yes
20-lead PLCC
Yes
44-lead TQFP
AT17F080
Yes
Yes
Yes
3039K–CNFG–2/08




AT17F080 pdf, 반도체, 판매, 대치품
3. Block Diagram
www.DataSheet4U.com
READY
PAGE_EN
PAGESEL0
PAGESEL1
Power-on
Reset
Reset
Config. Page
Select
Clock/Oscillator
Logic
Serial Download Logic
Flash
Memory
CE/WE/OE
Data
Address
2-wire Serial Programming
Control Logic
CLK
CEO(A2)
DATA
CE
RESET/OE
SER_EN
4. Device Description
The control signals for the configuration memory device (CE, RESET/OE and CLK) interface
directly with the FPGA device control signals. All FPGA devices can control the entire configura-
tion process and retrieve data from the configuration device without requiring an external
intelligent controller.
The RESET/OE and CE pins control the tri-state buffer on the DATA output pin and enable the
address counter. When RESET/OE is driven Low, the configuration device resets its address
counter and tri-states its DATA pin. The CE pin also controls the output of the AT17F Series
Configurator. If CE is held High after the RESET/OE reset pulse, the counter is disabled and the
DATA output pin is tri-stated. When OE is subsequently driven High, the counter and the DATA
output pin are enabled. When RESET/OE is driven Low again, the address counter is reset and
the DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device tri-states
the DATA pin to avoid contention with other configurators. Upon power-up, the address counter
is automatically reset.
4 AT17F040/080
3039K–CNFG–2/08

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AT17F080 전자부품, 판매, 대치품
AT17F040/080
5.9 A2(1)
www.DataSheet4U.com
Device selection input, (when SER_EN Low). The input is used to enable (or chip select) the
device during programming (i.e., when SER_EN is Low). Refer to the AT17F Programming
Specification available on the Atmel web site for additional details.
5.10 READY
5.11 SER_EN(1)
5.12 VCC
Open collector reset state indicator. Driven Low during power-up reset, released when power-up
is complete. (recommended 4.7 kpull-up on this pin if used).
The serial enable input must remain High during FPGA configuration operations. Bringing
SER_EN Low enables the 2-Wire Serial Programming Mode. For non-ISP applications,
SER_EN should be tied to VCC.
+3.3V (±10%).
Notes: 1. This pin has an internal 20 kpull-up resistor.
2. This pin has an internal 30 kpull-down resistor.
3039K–CNFG–2/08
7

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관련 데이터시트

부품번호상세설명 및 기능제조사
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(AT17F040 / AT17F080) FPGA Configuration Flash Memory

ATMEL Corporation
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